Simulation Results: edn/edn1

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.46 %
  • code
  • 82.20 %
  • assert
  • 97.14 %
  • func
  • 80.04 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 89.23 %
  • toggle
  • 86.33 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 35.652us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 68.357us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 13.573us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.480s 115.321us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 96.624us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.120s 31.381us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 13.573us 1 1 100.00
edn_csr_aliasing 0.950s 96.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 39.812us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 39.812us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 39.812us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.820s 38.771us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.870s 75.857us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 20.053us 1 1 100.00
disable 2 2 100.00
edn_disable 0.840s 14.293us 1 1 100.00
edn_disable_auto_req_mode 0.860s 22.821us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.530s 184.378us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 48.850us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.910s 30.746us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.210s 188.085us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.210s 188.085us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 68.357us 1 1 100.00
edn_csr_rw 0.730s 13.573us 1 1 100.00
edn_csr_aliasing 0.950s 96.624us 1 1 100.00
edn_same_csr_outstanding 0.810s 50.781us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 68.357us 1 1 100.00
edn_csr_rw 0.730s 13.573us 1 1 100.00
edn_csr_aliasing 0.950s 96.624us 1 1 100.00
edn_same_csr_outstanding 0.810s 50.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.000s 132.869us 1 1 100.00
edn_tl_intg_err 1.690s 737.034us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 18.113us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.870s 75.857us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.000s 132.869us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.000s 132.869us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.000s 132.869us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.000s 132.869us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.870s 75.857us 1 1 100.00
edn_sec_cm 2.000s 132.869us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.870s 75.857us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.690s 737.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 33.660s 7713.621us 1 1 100.00