Simulation Results: flash_ctrl

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.58 %
  • code
  • 94.49 %
  • assert
  • 96.67 %
  • func
  • 95.57 %
  • line
  • 95.98 %
  • branch
  • 97.10 %
  • cond
  • 93.73 %
  • toggle
  • 97.21 %
  • FSM
  • 88.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 35.100s 46.783us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 15.230s 88.354us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.650s 37.025us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 23.810s 1323.593us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.910s 2548.326us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.170s 43.809us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
flash_ctrl_csr_aliasing 22.910s 2548.326us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.220s 50.224us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.990s 25.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.960s 46.697us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 30.250s 154.229us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1194.460s 91504.536us 1 1 100.00
flash_ctrl_hw_rma_reset 606.280s 90156.396us 1 1 100.00
flash_ctrl_lcmgr_intg 5.600s 41.319us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1398.410s 388353.381us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 272.640s 27967.899us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.370s 35.995us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2579.240s 97828.841us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 78.630s 706.116us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 20.210s 83.352us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.640s 32.909us 1 1 100.00
flash_ctrl_re_evict 15.080s 71.808us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 22.890s 30.953us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 22.890s 30.953us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 172.450s 21315.477us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.830s 409.623us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 185.860s 1718.708us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 447.780s 69085.003us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 313.410s 726.912us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 608.330s 356.993us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.200s 22.155us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 142.950s 1342.659us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.690s 32.302us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.630s 73.385us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 82.060s 134.359us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 24.750s 2882.921us 1 1 100.00
flash_ctrl_otp_reset 54.480s 42.443us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1194.460s 91504.536us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 161.530s 3545.544us 1 1 100.00
flash_ctrl_intr_wr 49.810s 11191.263us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 104.690s 48336.824us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 184.340s 57033.175us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 35.470s 1800.126us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.200s 1289.464us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.370s 216.012us 1 1 100.00
flash_ctrl_ro_derr 96.200s 2541.944us 1 1 100.00
flash_ctrl_rw_derr 186.910s 2114.220us 1 1 100.00
flash_ctrl_derr_detect 110.950s 851.561us 1 1 100.00
flash_ctrl_integrity 452.840s 3855.371us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.310s 35.912us 1 1 100.00
flash_ctrl_ro_serr 111.920s 808.912us 1 1 100.00
flash_ctrl_rw_serr 177.060s 8249.417us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 52.730s 3348.911us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 73.620s 2181.486us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 93.200s 2094.873us 1 1 100.00
flash_ctrl_write_word_sweep 7.300s 37.834us 1 1 100.00
flash_ctrl_read_word_sweep 9.930s 98.118us 1 1 100.00
flash_ctrl_ro 72.250s 442.648us 1 1 100.00
flash_ctrl_rw 413.320s 13968.326us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.690s 333.550us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 607.920s 165725.538us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 115.360s 10031.640us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.590s 32.346us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.050s 17.836us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.140s 89.621us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.140s 89.621us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.650s 37.025us 1 1 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
flash_ctrl_csr_aliasing 22.910s 2548.326us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.350s 715.229us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.650s 37.025us 1 1 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
flash_ctrl_csr_aliasing 22.910s 2548.326us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.350s 715.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 22.630s 56.973us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
flash_ctrl_tl_intg_err 274.700s 353.103us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 274.700s 353.103us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 274.700s 353.103us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.350s 116.717us 1 1 100.00
flash_ctrl_wr_intg 6.650s 46.888us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 35.100s 46.783us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 54.480s 42.443us 1 1 100.00
flash_ctrl_disable 8.690s 32.302us 1 1 100.00
flash_ctrl_sec_info_access 42.540s 2731.946us 1 1 100.00
flash_ctrl_connect 5.630s 73.385us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.490s 74.257us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.120s 734.267us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.590s 74.240us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.690s 32.302us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.350s 116.717us 1 1 100.00
flash_ctrl_access_after_disable 5.500s 34.385us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 17.320s 27.565us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.690s 32.302us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.830s 409.623us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 413.320s 13968.326us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 177.060s 8249.417us 1 1 100.00
flash_ctrl_rw_derr 186.910s 2114.220us 1 1 100.00
flash_ctrl_integrity 452.840s 3855.371us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1194.460s 91504.536us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.270s 916.517us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 9.870s 22.846us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 5.940s 147.253us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1513.970s 5783.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.790s 140.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 348.100s 968.425us 1 1 100.00