Simulation Results: hmac

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.32 %
  • code
  • 97.23 %
  • assert
  • 96.70 %
  • func
  • 44.02 %
  • line
  • 99.59 %
  • branch
  • 99.17 %
  • cond
  • 96.23 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.040s 667.479us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.900s 24.366us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 106.001us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.680s 2098.486us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.390s 612.861us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.260s 55.594us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 106.001us 1 1 100.00
hmac_csr_aliasing 4.390s 612.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 21.280s 6346.920us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 42.830s 3981.291us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 177.750s 4811.048us 1 1 100.00
hmac_test_sha384_vectors 19.560s 933.210us 1 1 100.00
hmac_test_sha512_vectors 20.450s 238.588us 1 1 100.00
hmac_test_hmac256_vectors 7.630s 894.529us 1 1 100.00
hmac_test_hmac384_vectors 7.510s 3838.159us 1 1 100.00
hmac_test_hmac512_vectors 9.880s 591.554us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.220s 460.098us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 326.270s 5720.239us 1 1 100.00
error 1 1 100.00
hmac_error 24.750s 572.003us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 57.050s 2993.847us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.040s 667.479us 1 1 100.00
hmac_long_msg 21.280s 6346.920us 1 1 100.00
hmac_back_pressure 42.830s 3981.291us 1 1 100.00
hmac_datapath_stress 326.270s 5720.239us 1 1 100.00
hmac_burst_wr 19.220s 460.098us 1 1 100.00
hmac_stress_all 807.380s 81153.904us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.040s 667.479us 1 1 100.00
hmac_long_msg 21.280s 6346.920us 1 1 100.00
hmac_back_pressure 42.830s 3981.291us 1 1 100.00
hmac_datapath_stress 326.270s 5720.239us 1 1 100.00
hmac_wipe_secret 57.050s 2993.847us 1 1 100.00
hmac_test_sha256_vectors 177.750s 4811.048us 1 1 100.00
hmac_test_sha384_vectors 19.560s 933.210us 1 1 100.00
hmac_test_sha512_vectors 20.450s 238.588us 1 1 100.00
hmac_test_hmac256_vectors 7.630s 894.529us 1 1 100.00
hmac_test_hmac384_vectors 7.510s 3838.159us 1 1 100.00
hmac_test_hmac512_vectors 9.880s 591.554us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.040s 667.479us 1 1 100.00
hmac_long_msg 21.280s 6346.920us 1 1 100.00
hmac_back_pressure 42.830s 3981.291us 1 1 100.00
hmac_datapath_stress 326.270s 5720.239us 1 1 100.00
hmac_burst_wr 19.220s 460.098us 1 1 100.00
hmac_error 24.750s 572.003us 1 1 100.00
hmac_wipe_secret 57.050s 2993.847us 1 1 100.00
hmac_test_sha256_vectors 177.750s 4811.048us 1 1 100.00
hmac_test_sha384_vectors 19.560s 933.210us 1 1 100.00
hmac_test_sha512_vectors 20.450s 238.588us 1 1 100.00
hmac_test_hmac256_vectors 7.630s 894.529us 1 1 100.00
hmac_test_hmac384_vectors 7.510s 3838.159us 1 1 100.00
hmac_test_hmac512_vectors 9.880s 591.554us 1 1 100.00
hmac_stress_all 807.380s 81153.904us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 807.380s 81153.904us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 47.724us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 84.766us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.070s 267.713us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.070s 267.713us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.900s 24.366us 1 1 100.00
hmac_csr_rw 1.000s 106.001us 1 1 100.00
hmac_csr_aliasing 4.390s 612.861us 1 1 100.00
hmac_same_csr_outstanding 1.000s 257.204us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.900s 24.366us 1 1 100.00
hmac_csr_rw 1.000s 106.001us 1 1 100.00
hmac_csr_aliasing 4.390s 612.861us 1 1 100.00
hmac_same_csr_outstanding 1.000s 257.204us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.020s 124.279us 1 1 100.00
hmac_tl_intg_err 2.540s 366.936us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.540s 366.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.040s 667.479us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.760s 228.272us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 23.760s 14965.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.320s 534.643us 1 1 100.00