Simulation Results

Simulation Results: i2c

07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.22 %

code
81.50 %

assert
95.98 %

func
81.18 %

line
96.51 %

branch
92.33 %

cond
84.93 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	17.400s	3089.268us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	4.460s	362.942us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.780s	29.759us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.780s	57.716us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.010s	64.341us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.180s	117.609us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.910s	45.476us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.780s	57.716us	1	1	100.00
	i2c_csr_aliasing	1.180s	117.609us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.750s	14.922us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1205.100s	71102.163us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	26.580s	6711.495us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.800s	30.507us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	35.570s	2806.466us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	40.090s	3359.373us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.360s	528.581us	1	1	100.00
	i2c_host_fifo_fmt_empty	9.070s	262.512us	1	1	100.00
	i2c_host_fifo_reset_rx	4.450s	269.056us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	82.700s	13796.563us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	4.120s	692.850us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.590s	291.028us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.260s	1734.228us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	576.690s	42423.603us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.690s	901.691us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	10.460s	845.369us	1	1	100.00
	i2c_target_intr_smoke	5.930s	3755.517us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.340s	197.817us	1	1	100.00
	i2c_target_fifo_reset_tx	1.670s	291.440us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	7.500s	8889.547us	1	1	100.00
	i2c_target_stress_rd	10.460s	845.369us	1	1	100.00
	i2c_target_intr_stress_wr	21.610s	16490.228us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.780s	6418.535us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	7.390s	10005.028us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.490s	2363.536us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.780s	226.875us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.550s	1534.589us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.240s	1336.255us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	26.580s	6711.495us	1	1	100.00
	i2c_host_perf_precise	10.890s	3730.766us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	4.120s	692.850us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	6.300s	593.043us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.310s	856.727us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.720s	479.002us	1	1	100.00
	i2c_target_nack_txstretch	1.150s	605.895us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.110s	1004.175us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.190s	505.166us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.770s	16.615us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.750s	21.990us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.970s	386.525us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.970s	386.525us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.780s	29.759us	1	1	100.00
	i2c_csr_rw	0.780s	57.716us	1	1	100.00
	i2c_csr_aliasing	1.180s	117.609us	1	1	100.00
	i2c_same_csr_outstanding	0.850s	41.305us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.780s	29.759us	1	1	100.00
	i2c_csr_rw	0.780s	57.716us	1	1	100.00
	i2c_csr_aliasing	1.180s	117.609us	1	1	100.00
	i2c_same_csr_outstanding	0.850s	41.305us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.060s	89.877us	1	1	100.00
	i2c_sec_cm	1.080s	583.907us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.060s	89.877us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.350s	1164.450us	1
target_error_intr				1
	i2c_target_unexp_stop	1.310s	61.264us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	9.670s	4934.944us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	32622514429076090491689344446562752199844338857903995697805778054884087331629	80	UVM_INFO @ 14922096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	40888606074564142445177049077392158617447624068346725029945783651943971162363	96	UVM_INFO @ 4934943537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_stress_all	54250089087177591056858194080096204496340293477328169557052048007849341533311	157	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @12512124
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	7538687808218041738968985408545764500615169797700767289236568755712044056669	84	UVM_INFO @ 1734227556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	68299934065549917439946227841940011483417734098723494151102101752430961590789	78	UVM_INFO @ 10005027870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	81193057696398095778746228405684887850739358653289616350737924263256469592835	79	UVM_ERROR @ 61264487 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 61264487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	80188748948927185859222507304153505011936581922401204029748095659079875829781	95	UVM_INFO @ 1164449509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	22537431263976397741055593728606456840268425369783528896948663312168483823959	78	UVM_INFO @ 605894573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---