Simulation Results: kmac/unmasked

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.04 %
  • code
  • 88.00 %
  • assert
  • 97.75 %
  • func
  • 93.36 %
  • line
  • 97.11 %
  • branch
  • 94.46 %
  • cond
  • 91.51 %
  • toggle
  • 99.92 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 23.590s 1312.666us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.060s 20.564us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.030s 79.339us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.370s 1873.243us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.830s 525.071us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.380s 41.928us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.030s 79.339us 1 1 100.00
kmac_csr_aliasing 7.830s 525.071us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.950s 17.182us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.520s 20.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1759.420s 81043.824us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 461.260s 33984.910us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1696.990s 246271.776us 1 1 100.00
kmac_test_vectors_sha3_256 1220.840s 16808.836us 1 1 100.00
kmac_test_vectors_sha3_384 21.350s 1208.444us 1 1 100.00
kmac_test_vectors_sha3_512 10.500s 657.543us 1 1 100.00
kmac_test_vectors_shake_128 145.200s 9782.836us 1 1 100.00
kmac_test_vectors_shake_256 89.790s 15269.040us 1 1 100.00
kmac_test_vectors_kmac 1.800s 64.135us 1 1 100.00
kmac_test_vectors_kmac_xof 1.560s 97.929us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 34.450s 8471.133us 1 1 100.00
app 1 1 100.00
kmac_app 21.150s 1579.708us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 149.080s 8540.700us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 156.870s 4020.261us 1 1 100.00
error 1 1 100.00
kmac_error 173.380s 3543.881us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.490s 1554.049us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 22.410s 10039.228us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 20.560s 14947.025us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 11.510s 3270.798us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 46.570s 6254.224us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.720s 206.478us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 619.000s 10714.135us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.920s 65.655us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.990s 28.586us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.140s 153.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.140s 153.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.060s 20.564us 1 1 100.00
kmac_csr_rw 1.030s 79.339us 1 1 100.00
kmac_csr_aliasing 7.830s 525.071us 1 1 100.00
kmac_same_csr_outstanding 1.580s 68.595us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.060s 20.564us 1 1 100.00
kmac_csr_rw 1.030s 79.339us 1 1 100.00
kmac_csr_aliasing 7.830s 525.071us 1 1 100.00
kmac_same_csr_outstanding 1.580s 68.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.650s 40.454us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.650s 40.454us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.650s 40.454us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.650s 40.454us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.140s 597.400us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 26.590s 2869.363us 1 1 100.00
kmac_tl_intg_err 4.180s 901.409us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.180s 901.409us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.720s 206.478us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 23.590s 1312.666us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 34.450s 8471.133us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.650s 40.454us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 26.590s 2869.363us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 26.590s 2869.363us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 26.590s 2869.363us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 23.590s 1312.666us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.720s 206.478us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 26.590s 2869.363us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 129.100s 9227.070us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 23.590s 1312.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 27.630s 1312.704us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
kmac_sideload_invalid 7967414769526961738401457265741759611839556077162143426306299276970047167269 78
UVM_INFO @ 10039227819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 50202705848237269776743337703306282366217996748164250672562776653221489497407 168
UVM_INFO @ 1312703680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---