Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.93 %
  • code
  • 84.53 %
  • assert
  • 94.13 %
  • func
  • 94.13 %
  • line
  • 97.24 %
  • branch
  • 93.85 %
  • cond
  • 79.31 %
  • toggle
  • 88.68 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.600s 244.129us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 22.381us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.220s 32.087us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.150s 57.189us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 29.072us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 26.870us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.220s 32.087us 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 29.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.180s 61.396us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.570s 1773.945us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 95.209us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.700s 511.155us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.340s 1945.380us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_prog_failure 2.700s 511.155us 1 1 100.00
lc_ctrl_errors 9.340s 1945.380us 1 1 100.00
lc_ctrl_security_escalation 8.970s 602.064us 1 1 100.00
lc_ctrl_jtag_state_failure 23.830s 2061.398us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.670s 1670.389us 1 1 100.00
lc_ctrl_jtag_errors 53.590s 3036.490us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.670s 181.054us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.580s 1224.013us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.670s 1670.389us 1 1 100.00
lc_ctrl_jtag_errors 53.590s 3036.490us 1 1 100.00
lc_ctrl_jtag_access 5.450s 257.540us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.780s 2869.624us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.710s 787.170us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.390s 185.551us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.610s 1891.851us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.320s 356.751us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.400s 18.315us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.080s 639.979us 1 1 100.00
lc_ctrl_jtag_alert_test 0.870s 152.939us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.640s 815.243us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.210s 18.440us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 18.440s 1284.634us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.140s 20.829us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 112.376us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 112.376us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 22.381us 1 1 100.00
lc_ctrl_csr_rw 1.220s 32.087us 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 29.072us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.430s 25.380us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 22.381us 1 1 100.00
lc_ctrl_csr_rw 1.220s 32.087us 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 29.072us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.430s 25.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
lc_ctrl_tl_intg_err 1.240s 50.259us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.240s 50.259us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.570s 1773.945us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.550s 556.756us 1 1 100.00
lc_ctrl_sec_cm 7.910s 1008.703us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.970s 602.064us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.180s 61.396us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.580s 1224.013us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 14.000s 904.592us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 14.000s 904.592us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.140s 264.917us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.540s 269.109us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.540s 269.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 57.670s 24594.914us 1 1 100.00