Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.20 %
  • code
  • 83.93 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.08 %
  • branch
  • 93.23 %
  • cond
  • 78.87 %
  • toggle
  • 88.79 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.240s 15.578us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 15.462us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 45.623us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.730s 877.682us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 144.859us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.230s 34.061us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 45.623us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 144.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.020s 67.803us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.140s 333.261us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.930s 37.724us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.460s 124.675us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.460s 480.247us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_prog_failure 2.460s 124.675us 1 1 100.00
lc_ctrl_errors 6.460s 480.247us 1 1 100.00
lc_ctrl_security_escalation 8.330s 573.895us 1 1 100.00
lc_ctrl_jtag_state_failure 42.740s 8329.918us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.420s 299.188us 1 1 100.00
lc_ctrl_jtag_errors 29.500s 21930.381us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 9.260s 1089.030us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.580s 2203.893us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.420s 299.188us 1 1 100.00
lc_ctrl_jtag_errors 29.500s 21930.381us 1 1 100.00
lc_ctrl_jtag_access 5.840s 1076.998us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.400s 2290.736us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.720s 1225.409us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.550s 378.296us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.610s 4619.468us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.650s 1485.017us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 73.927us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.700s 242.712us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 35.777us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.320s 1301.337us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 168.240us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 67.480s 5703.792us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 73.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.310s 76.059us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.310s 76.059us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 15.462us 1 1 100.00
lc_ctrl_csr_rw 0.850s 45.623us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 144.859us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 53.517us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 15.462us 1 1 100.00
lc_ctrl_csr_rw 0.850s 45.623us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 144.859us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 53.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 84.414us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 84.414us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.140s 333.261us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.330s 200.609us 1 1 100.00
lc_ctrl_sec_cm 8.640s 1227.148us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.330s 573.895us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.020s 67.803us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.580s 2203.893us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.420s 2595.603us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.420s 2595.603us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.490s 2263.612us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.810s 258.954us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.810s 258.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 38.700s 11381.412us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 31030159958875339627004104869925230799570817690507181525798733275447745927278 4329
UVM_INFO @ 11381411624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---