Simulation Results: otbn

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.69 %
  • code
  • 95.52 %
  • assert
  • 89.78 %
  • func
  • 95.76 %
  • block
  • 99.45 %
  • line
  • 99.59 %
  • branch
  • 92.99 %
  • toggle
  • 92.05 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 72.170us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 32.000s 27.549us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 32.000s 12.162us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 34.000s 477.036us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 32.000s 14.815us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 34.000s 30.082us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 32.000s 12.162us 1 1 100.00
otbn_csr_aliasing 32.000s 14.815us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 76.000s 4723.242us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 2929.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 84.233us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 41.000s 300.238us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 49.000s 404.696us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 33.000s 513.286us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 31.000s 34.346us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 6.000s 10.879us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 40.760us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 36.000s 37.836us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 20.000s 27.115us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 273.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 273.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 32.000s 27.549us 1 1 100.00
otbn_csr_rw 32.000s 12.162us 1 1 100.00
otbn_csr_aliasing 32.000s 14.815us 1 1 100.00
otbn_same_csr_outstanding 4.000s 66.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 32.000s 27.549us 1 1 100.00
otbn_csr_rw 32.000s 12.162us 1 1 100.00
otbn_csr_aliasing 32.000s 14.815us 1 1 100.00
otbn_same_csr_outstanding 4.000s 66.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 23.000s 50.477us 1 1 100.00
otbn_dmem_err 31.000s 66.466us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 35.000s 209.883us 1 1 100.00
otbn_controller_ispr_rdata_err 37.000s 60.229us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 98.625us 1 1 100.00
otbn_urnd_err 6.000s 57.188us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 29.000s 26.709us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 19.734us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 31.478us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
otbn_tl_intg_err 10.000s 77.849us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 5.000s 44.298us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 72.170us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 31.000s 66.466us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 23.000s 50.477us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 77.849us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 31.000s 34.346us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 23.000s 50.477us 1 1 100.00
otbn_dmem_err 31.000s 66.466us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.879us 0 1 0.00
otbn_illegal_mem_acc 29.000s 26.709us 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 23.000s 50.477us 1 1 100.00
otbn_dmem_err 31.000s 66.466us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.879us 0 1 0.00
otbn_illegal_mem_acc 29.000s 26.709us 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 31.000s 34.346us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 23.000s 50.477us 1 1 100.00
otbn_dmem_err 31.000s 66.466us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.879us 0 1 0.00
otbn_illegal_mem_acc 29.000s 26.709us 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 34.000s 64.020us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 104.677us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 20.000s 155.389us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 20.000s 155.389us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 17.264us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 56.852us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 118.158us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 118.158us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 13.446us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 49.000s 404.696us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 40.334us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 92.387us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 174.000s 1021.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 53.000s 247.793us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 20.415us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 38875533019470233140235419371578382862740515120784433361522109533451931407584 194
UVM_INFO @ 247792747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
otbn_zero_state_err_urnd 59110835436945573815617013736417353063856277799498284634167884820295390519155 105
UVM_INFO @ 10879322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
otbn_urnd_err 52116761017699824978927258551616825031654588309389597266238268557534713525664 108
UVM_INFO @ 57188066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 95168624460490757376583969066874643532200664001907067836497193901467075581719 91
UVM_INFO @ 44298315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---