Simulation Results: otp_ctrl

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.55 %
  • code
  • 75.35 %
  • assert
  • 93.79 %
  • func
  • 66.52 %
  • line
  • 88.45 %
  • branch
  • 82.89 %
  • cond
  • 89.72 %
  • toggle
  • 74.53 %
  • FSM
  • 41.15 %
Validation stages
V1
100.00%
V2
85.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.440s 104.853us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.630s 248.771us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.590s 112.582us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.060s 232.877us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 212.336us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.910s 402.633us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.590s 112.582us 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 212.336us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.190s 43.866us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.190s 144.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.950s 5044.358us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.740s 2439.403us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 15.190s 1552.454us 0 1 0.00
otp_ctrl_check_fail 3.760s 190.920us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.830s 801.441us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 17.860s 2560.124us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.140s 920.291us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 29.810s 9190.879us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.740s 61.400us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 21.220s 8936.535us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 11.520s 1596.741us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.680s 137.284us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.390s 63.071us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.030s 134.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.030s 134.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.630s 248.771us 1 1 100.00
otp_ctrl_csr_rw 1.590s 112.582us 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 212.336us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.740s 2016.269us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.630s 248.771us 1 1 100.00
otp_ctrl_csr_rw 1.590s 112.582us 1 1 100.00
otp_ctrl_csr_aliasing 4.500s 212.336us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.740s 2016.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
otp_ctrl_tl_intg_err 7.720s 649.060us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.720s 649.060us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_ctrl_macro_errs 1.740s 61.400us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_ctrl_macro_errs 1.740s 61.400us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.200s 53.377us 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.740s 2439.403us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 3.760s 190.920us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.000s 379.261us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.100s 17579.473us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.830s 801.441us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.680s 144.992us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.740s 61.400us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 14.260s 7500.580us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.140s 110.630us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 2 test runs
otp_ctrl_background_chks 11331047466131728103250063378995935907409831147959011530120889566577898046690 21041
UVM_INFO @ 1552453944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 41395904401490022963514869290958692906753318773087771302961060853018684988975 12440
UVM_INFO @ 1596741265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 95073780424681504836189244383931963696049722885709230229213094539876564367655 233
UVM_INFO @ 61399874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 44545009309133896262912071908331271045128067820773847841029950350729572987358 92
UVM_INFO @ 110630120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---