Simulation Results: pattgen

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 135.915us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 60.369us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 61.142us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 638.791us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 53.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 75.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 61.142us 1 1 100.00
pattgen_csr_aliasing 2.000s 53.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 10.000s 2206.936us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 12.000s 5278.253us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 77.144us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 3.000s 802.542us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 16.330us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 16.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 68.058us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 68.058us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 60.369us 1 1 100.00
pattgen_csr_rw 1.000s 61.142us 1 1 100.00
pattgen_csr_aliasing 2.000s 53.474us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 134.112us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 60.369us 1 1 100.00
pattgen_csr_rw 1.000s 61.142us 1 1 100.00
pattgen_csr_aliasing 2.000s 53.474us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 134.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 85.484us 1 1 100.00
pattgen_sec_cm 2.000s 143.519us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 85.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 20.000s 4899.619us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 205.551us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 107559036397327222825157071316052192129042521940361036498270564738092953002913 335
UVM_ERROR @ 4880026600 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4880026600 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 4880210272 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: 1 test run
pattgen_stress_all 53122555913307525293283303446841743566128258382985928586565357469333941029013 146
-----------------------------------
Name Type Size Value
-----------------------------------
exp_item pattgen_item - @1723