Simulation Results: pwrmgr

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 94.45 %
  • assert
  • 95.04 %
  • func
  • 97.20 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.63 %
  • toggle
  • 89.08 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.750s 22.490us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.720s 39.207us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 65.442us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.300s 80.717us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.682us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.080s 111.711us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 65.442us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.620s 103.361us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.620s 103.361us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.840s 26.225us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 47.012us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.670s 50.341us 1 1 100.00
pwrmgr_reset_invalid 0.810s 98.942us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.670s 50.341us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.590s 78.533us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.680s 80.696us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.750s 113.083us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 20.250s 10821.606us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 27.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.320s 236.619us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.320s 236.619us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.720s 39.207us 1 1 100.00
pwrmgr_csr_rw 0.630s 65.442us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.682us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 24.381us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.720s 39.207us 1 1 100.00
pwrmgr_csr_rw 0.630s 65.442us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 21.682us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 24.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.630s 8.513us 0 1 0.00
pwrmgr_sec_cm 0.720s 28.052us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.720s 28.052us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.720s 28.052us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.630s 8.513us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.460s 1226.277us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.590s 78.533us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.840s 148.840us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 59.290us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.720s 28.052us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.720s 28.052us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.720s 28.052us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.610s 215.882us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.650s 62.763us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.730s 201.425us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 65.442us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 65.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.770s 374.344us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 10.920s 12488.614us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
pwrmgr_tl_intg_err 58839670472014497840500378517454900794459976493036158311391763276476135719256 78
UVM_INFO @ 8512958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 36757507944292364865964649412977510147152273826462743728094191557134073167803 86
UVM_INFO @ 28051687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 110398138629149772482591965118605289412083916333166804170094636604814744455578 780
UVM_INFO @ 10821605711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---