Simulation Results: rom_ctrl/32kb

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.02 %
  • code
  • 97.75 %
  • assert
  • 96.66 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.33 %
  • toggle
  • 99.34 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.140s 136.724us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.370s 127.313us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.520s 605.615us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.320s 209.760us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 557.597us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.980s 760.691us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.520s 605.615us 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 557.597us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.330s 212.381us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.790s 555.806us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.150s 3141.903us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.520s 343.543us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.270s 3605.106us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.100s 166.470us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.820s 497.829us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.820s 497.829us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.370s 127.313us 1 1 100.00
rom_ctrl_csr_rw 3.520s 605.615us 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 557.597us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.250s 337.465us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.370s 127.313us 1 1 100.00
rom_ctrl_csr_rw 3.520s 605.615us 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 557.597us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.250s 337.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.060s 3314.874us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 95.810s 852.151us 1 1 100.00
rom_ctrl_tl_intg_err 23.260s 200.574us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 95.810s 852.151us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 95.810s 852.151us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 95.810s 852.151us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 95.810s 852.151us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.140s 136.724us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.140s 136.724us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.140s 136.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.260s 200.574us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
rom_ctrl_kmac_err_chk 7.270s 3605.106us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.760s 5238.853us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.060s 3314.874us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 95.810s 852.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 46.440s 1748.996us 1 1 100.00