Simulation Results: rom_ctrl/64kb

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.14 %
  • code
  • 97.95 %
  • assert
  • 96.80 %
  • func
  • 96.66 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 98.37 %
  • toggle
  • 99.21 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.570s 522.563us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.110s 518.291us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.900s 212.774us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.870s 377.935us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.110s 292.085us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.110s 1094.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.900s 212.774us 1 1 100.00
rom_ctrl_csr_aliasing 8.110s 292.085us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.080s 651.348us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.570s 1213.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.680s 739.250us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 29.950s 12620.093us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.710s 2958.544us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.670s 1026.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.620s 300.185us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.620s 300.185us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.110s 518.291us 1 1 100.00
rom_ctrl_csr_rw 5.900s 212.774us 1 1 100.00
rom_ctrl_csr_aliasing 8.110s 292.085us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.700s 1019.489us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.110s 518.291us 1 1 100.00
rom_ctrl_csr_rw 5.900s 212.774us 1 1 100.00
rom_ctrl_csr_aliasing 8.110s 292.085us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.700s 1019.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.290s 17933.963us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 438.470s 2671.699us 1 1 100.00
rom_ctrl_tl_intg_err 48.740s 1120.222us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 438.470s 2671.699us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 438.470s 2671.699us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 438.470s 2671.699us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 438.470s 2671.699us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.570s 522.563us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.570s 522.563us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.570s 522.563us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 48.740s 1120.222us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
rom_ctrl_kmac_err_chk 13.710s 2958.544us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.020s 2722.907us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.290s 17933.963us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 438.470s 2671.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 210.430s 3224.687us 1 1 100.00