Simulation Results: rstmgr

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 99.19 %
  • assert
  • 97.86 %
  • func
  • 95.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.61 %
  • toggle
  • 98.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.090s 201.536us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.940s 147.456us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.890s 86.737us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.960s 488.875us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.090s 405.239us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.100s 135.654us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.890s 86.737us 1 1 100.00
rstmgr_csr_aliasing 2.090s 405.239us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.820s 214.106us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.100s 454.455us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.880s 75.205us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 2.860s 844.751us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 2.860s 844.751us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 2.860s 844.751us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 2.860s 844.751us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 44.300s 17629.912us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.670s 58.412us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.220s 111.701us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.220s 111.701us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 147.456us 1 1 100.00
rstmgr_csr_rw 0.890s 86.737us 1 1 100.00
rstmgr_csr_aliasing 2.090s 405.239us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 141.990us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 147.456us 1 1 100.00
rstmgr_csr_rw 0.890s 86.737us 1 1 100.00
rstmgr_csr_aliasing 2.090s 405.239us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 141.990us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.410s 16856.032us 1 1 100.00
rstmgr_tl_intg_err 1.620s 445.572us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.410s 16856.032us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.410s 16856.032us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.620s 445.572us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.850s 99.737us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.480s 2449.796us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.010s 302.201us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.410s 16856.032us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 86.737us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 86.737us 1 1 100.00