Simulation Results: rv_timer

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.11 %
  • code
  • 99.92 %
  • assert
  • 95.54 %
  • func
  • 95.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.900s 142.026us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.690s 17.472us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 13.888us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.380s 171.496us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.760s 66.857us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 46.415us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 13.888us 1 1 100.00
rv_timer_csr_aliasing 0.760s 66.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.090s 375.055us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.760s 1158.487us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 207.480s 304115.608us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 207.480s 304115.608us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.680s 5647.053us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 13.044us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.570s 14.183us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.600s 44.920us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.600s 44.920us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.690s 17.472us 1 1 100.00
rv_timer_csr_rw 0.580s 13.888us 1 1 100.00
rv_timer_csr_aliasing 0.760s 66.857us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 17.261us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.690s 17.472us 1 1 100.00
rv_timer_csr_rw 0.580s 13.888us 1 1 100.00
rv_timer_csr_aliasing 0.760s 66.857us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 17.261us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.870s 357.189us 1 1 100.00
rv_timer_tl_intg_err 0.790s 55.428us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.790s 55.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.740s 204.225us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.590s 115.105us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 37.340s 4517.686us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 36646846628322483883772491117120918149416226953893496457286344928751336540438 75
UVM_INFO @ 204224992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 113086340603676787996860173584503141251683072684989304806301536350485616258202 76
UVM_INFO @ 375054511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 74554532625998185803724849027986568601806995915977964589267410653697787183406 76
UVM_INFO @ 115105158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---