Simulation Results: spi_device/1r1w

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.66 %
  • code
  • 93.15 %
  • assert
  • 92.89 %
  • func
  • 61.95 %
  • line
  • 99.03 %
  • branch
  • 98.20 %
  • cond
  • 95.62 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 24.120s 20996.409us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.240s 85.948us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.110s 18.526us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 14.290s 384.387us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.930s 631.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.210s 128.258us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.110s 18.526us 1 1 100.00
spi_device_csr_aliasing 10.930s 631.084us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.790s 35.235us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.080s 119.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.760s 22.987us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.830s 9.898us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.940s 3.259us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.940s 27.492us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.940s 27.492us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.460s 2297.251us 1 1 100.00
spi_device_tpm_sts_read 0.830s 72.999us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.500s 574.629us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.990s 3865.664us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.300s 15353.445us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.300s 15353.445us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.460s 404.766us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.460s 404.766us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.460s 404.766us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.460s 404.766us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.460s 404.766us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.380s 290.549us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 21.620s 2694.659us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 21.620s 2694.659us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 21.620s 2694.659us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 14.980s 2094.523us 1 1 100.00
spi_device_read_buffer_direct 7.230s 901.098us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 21.620s 2694.659us 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 27.490s 4291.460us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 9.490s 1312.628us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 9.490s 1312.628us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 24.120s 20996.409us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 76.190s 10554.363us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.980s 99.500us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.650s 20.725us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 17.520us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.980s 235.934us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.980s 235.934us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.240s 85.948us 1 1 100.00
spi_device_csr_rw 1.110s 18.526us 1 1 100.00
spi_device_csr_aliasing 10.930s 631.084us 1 1 100.00
spi_device_same_csr_outstanding 1.680s 26.831us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.240s 85.948us 1 1 100.00
spi_device_csr_rw 1.110s 18.526us 1 1 100.00
spi_device_csr_aliasing 10.930s 631.084us 1 1 100.00
spi_device_same_csr_outstanding 1.680s 26.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.310s 231.649us 1 1 100.00
spi_device_tl_intg_err 13.800s 2476.496us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 13.800s 2476.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 67.370s 46110.242us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 55186093260705636521135858315053019646665251290005912617678019848566945764987 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 8129253 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 8129253 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[997])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 50244249085926637552548770476152693236553790059686602986274742593806001492965 76
UVM_ERROR @ 956323 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x98c511 [100110001100010100010001] vs 0x0 [0])
UVM_ERROR @ 959323 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x69ed71 [11010011110110101110001] vs 0x0 [0])
UVM_ERROR @ 1035323 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x86ed59 [100001101110110101011001] vs 0x0 [0])
UVM_ERROR @ 1109323 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4ec481 [10011101100010010000001] vs 0x0 [0])