Simulation Results: spi_device/2p

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.49 %
  • code
  • 94.12 %
  • assert
  • 94.62 %
  • func
  • 70.73 %
  • line
  • 99.12 %
  • branch
  • 98.39 %
  • cond
  • 96.00 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 64.870s 12536.520us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.970s 25.619us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.440s 136.185us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.730s 2586.656us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.240s 657.962us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.960s 85.702us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.440s 136.185us 1 1 100.00
spi_device_csr_aliasing 6.240s 657.962us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.820s 13.814us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.760s 62.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.810s 15.773us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.250s 59.671us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.880s 22.853us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.430s 242.009us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.430s 242.009us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.490s 11249.354us 1 1 100.00
spi_device_tpm_sts_read 0.790s 106.789us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 21.600s 4339.464us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.790s 11108.405us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.230s 3796.897us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.230s 3796.897us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 13.680s 1739.400us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 13.680s 1739.400us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 13.680s 1739.400us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 13.680s 1739.400us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 13.680s 1739.400us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.860s 2683.798us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 21.800s 5969.903us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 21.800s 5969.903us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 21.800s 5969.903us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 13.610s 1315.543us 1 1 100.00
spi_device_read_buffer_direct 3.820s 541.560us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 21.800s 5969.903us 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 47.660s 3109.468us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.630s 270.633us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.630s 270.633us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 64.870s 12536.520us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 89.980s 7074.236us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 10.370s 1192.021us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.860s 24.443us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 14.568us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.650s 151.383us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.650s 151.383us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 25.619us 1 1 100.00
spi_device_csr_rw 1.440s 136.185us 1 1 100.00
spi_device_csr_aliasing 6.240s 657.962us 1 1 100.00
spi_device_same_csr_outstanding 2.230s 517.211us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 25.619us 1 1 100.00
spi_device_csr_rw 1.440s 136.185us 1 1 100.00
spi_device_csr_aliasing 6.240s 657.962us 1 1 100.00
spi_device_same_csr_outstanding 2.230s 517.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.240s 94.953us 1 1 100.00
spi_device_tl_intg_err 15.480s 876.880us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.480s 876.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 3.290s 574.723us 1 1 100.00