Simulation Results: sram_ctrl/main

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.04 %
  • code
  • 96.81 %
  • assert
  • 96.32 %
  • func
  • 95.00 %
  • block
  • 96.08 %
  • line
  • 96.81 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1412.451us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 17.270us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.308us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 462.932us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.757us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 370.652us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 41.308us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.757us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 235.000s 21785.800us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 51.000s 29602.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 42.000s 95903.407us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 169.000s 11029.565us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 116.000s 8703.532us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 17.000s 3371.138us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 40.000s 15298.913us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 31.000s 7035.714us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 3143.128us 1 1 100.00
sram_ctrl_partial_access_b2b 257.000s 19456.044us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 6778.107us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 729.094us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 13430.587us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 543.881us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1529.991us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 467.000s 53749.046us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 31.787us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 167.276us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 167.276us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 17.270us 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.308us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.757us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.228us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 17.270us 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.308us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 31.757us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 49.000s 140876.750us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1070.699us 1 1 100.00
sram_ctrl_tl_intg_err 5.000s 696.535us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1070.699us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 5.000s 696.535us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 543.881us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 543.881us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 41.308us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 31.000s 7035.714us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 7035.714us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 7035.714us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 40.000s 15298.913us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 671.317us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 49.000s 140876.750us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1281.481us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1412.451us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1412.451us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 31.000s 7035.714us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1070.699us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 40.000s 15298.913us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1070.699us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1070.699us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1412.451us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1070.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 1842.605us 1 1 100.00