Simulation Results: sram_ctrl/ret

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.74 %
  • code
  • 82.99 %
  • assert
  • 96.43 %
  • func
  • 92.80 %
  • block
  • 93.32 %
  • line
  • 94.44 %
  • branch
  • 88.58 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 122.410us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 29.012us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 3.000s 18.943us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 227.170us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.681us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 81.615us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 3.000s 18.943us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.681us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 76.916us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 177.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 822.382us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 166.000s 19060.184us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 109.066us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 22.000s 781.455us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 243.047us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 568.569us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 97.496us 1 1 100.00
sram_ctrl_partial_access_b2b 149.000s 10546.956us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 71.565us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 165.438us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 129.744us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 291.655us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 34.789us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 24.000s 4870.390us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 29.902us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 149.458us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 149.458us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 29.012us 1 1 100.00
sram_ctrl_csr_rw 3.000s 18.943us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.681us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.891us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 29.012us 1 1 100.00
sram_ctrl_csr_rw 3.000s 18.943us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.681us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 28.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 219.719us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 5663.308us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 166.391us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 5663.308us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 166.391us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 291.655us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 291.655us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 3.000s 18.943us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 568.569us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 568.569us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 568.569us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 243.047us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 120.824us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 219.719us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 36.123us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 122.410us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 122.410us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 568.569us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 5663.308us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 243.047us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 5663.308us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 5663.308us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 122.410us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 5663.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 698.345us 1 1 100.00