Simulation Results: sysrst_ctrl

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.84 %
  • code
  • 92.05 %
  • assert
  • 91.28 %
  • func
  • 71.19 %
  • line
  • 96.46 %
  • branch
  • 96.96 %
  • cond
  • 93.77 %
  • toggle
  • 100.00 %
  • FSM
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.740s 2110.939us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.500s 2509.448us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.960s 2417.178us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.570s 2506.950us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 8.450s 4012.617us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.710s 2034.696us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 124.310s 39075.139us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.240s 3287.187us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.570s 2088.414us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.710s 2034.696us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.240s 3287.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 68.830s 36480.653us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 222.240s 243914.746us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 179.070s 94186.456us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 0.960s 2871.920us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.910s 2527.321us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.850s 2257.471us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.260s 2794.682us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.180s 2619.282us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.250s 9361.684us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 37.360s 32290.113us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 24.420s 18442.563us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.460s 2041.589us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.110s 2022.847us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.890s 2206.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.890s 2206.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.450s 4012.617us 1 1 100.00
sysrst_ctrl_csr_rw 4.710s 2034.696us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.240s 3287.187us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 20.470s 10936.530us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.450s 4012.617us 1 1 100.00
sysrst_ctrl_csr_rw 4.710s 2034.696us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.240s 3287.187us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 20.470s 10936.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 5.710s 43056.899us 1 1 100.00
sysrst_ctrl_tl_intg_err 79.700s 42386.619us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 79.700s 42386.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.430s 20263.335us 1 1 100.00