Simulation Results: uart

 
07/05/2026 15:30:24 DVSim: v1.34.0 sha: 9bbcf3f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.16 %
  • code
  • 94.69 %
  • assert
  • 97.12 %
  • func
  • 51.68 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 92.07 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.470s 652.599us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.690s 19.486us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.680s 17.236us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.360s 37.412us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 16.855us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.800s 32.922us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.680s 17.236us 1 1 100.00
uart_csr_aliasing 0.800s 16.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 35.730s 115485.322us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.470s 652.599us 1 1 100.00
uart_tx_rx 35.730s 115485.322us 1 1 100.00
parity_error 2 2 100.00
uart_intr 101.820s 385088.646us 1 1 100.00
uart_rx_parity_err 48.660s 43515.951us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 35.730s 115485.322us 1 1 100.00
uart_intr 101.820s 385088.646us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 36.580s 116915.538us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 20.490s 47242.165us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 122.840s 221974.983us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 101.820s 385088.646us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 101.820s 385088.646us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 101.820s 385088.646us 1 1 100.00
perf 1 1 100.00
uart_perf 150.390s 10303.723us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.370s 8449.216us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.370s 8449.216us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.410s 7871.602us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.370s 30026.948us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.300s 7184.366us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.430s 1269.712us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 112.030s 68373.646us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 69.700s 66206.393us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.650s 48.184us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 13.555us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.850s 152.951us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.850s 152.951us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.690s 19.486us 1 1 100.00
uart_csr_rw 0.680s 17.236us 1 1 100.00
uart_csr_aliasing 0.800s 16.855us 1 1 100.00
uart_same_csr_outstanding 0.880s 50.915us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.690s 19.486us 1 1 100.00
uart_csr_rw 0.680s 17.236us 1 1 100.00
uart_csr_aliasing 0.800s 16.855us 1 1 100.00
uart_same_csr_outstanding 0.880s 50.915us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.270s 255.866us 1 1 100.00
uart_tl_intg_err 1.140s 115.180us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.140s 115.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 39.460s 1470.281us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 3 test runs
uart_noise_filter 14583359771653406230385805237584242745384454011252693048448295771612917006705 76
UVM_ERROR @ 3947442359 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 4283042359 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 4286562359 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 4286602359 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all_with_rand_reset 2563943146255852061872396614333628809180154273040715319744385873660273293188 116
UVM_ERROR @ 1390320534 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1390730534 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1391140534 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1391540534 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 94993613614991794066385857297624747202402005713582386319167346610776136152488 80
UVM_ERROR @ 17664129917 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 17672838320 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 17681546723 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 17690255126 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0