Simulation Results: adc_ctrl

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.74 %
  • code
  • 95.50 %
  • assert
  • 91.57 %
  • func
  • 13.14 %
  • line
  • 98.74 %
  • branch
  • 97.22 %
  • cond
  • 87.18 %
  • toggle
  • 99.76 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
57.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.790s 5769.170us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.770s 737.358us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.950s 487.342us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 46.730s 46499.586us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.360s 1081.079us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.260s 357.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.950s 487.342us 1 1 100.00
adc_ctrl_csr_aliasing 1.360s 1081.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.210s 345.351us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.760s 336.746us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.940s 517.968us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.990s 342.449us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.740s 405.799us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.860s 382.432us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.020s 372.094us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.980s 443.557us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.110s 4039.641us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 13.830s 35430.849us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 36.190s 87388.097us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 68.220s 167254.466us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.950s 375.932us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.010s 523.399us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.760s 519.685us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.760s 519.685us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.770s 737.358us 1 1 100.00
adc_ctrl_csr_rw 0.950s 487.342us 1 1 100.00
adc_ctrl_csr_aliasing 1.360s 1081.079us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.420s 4595.518us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.770s 737.358us 1 1 100.00
adc_ctrl_csr_rw 0.950s 487.342us 1 1 100.00
adc_ctrl_csr_aliasing 1.360s 1081.079us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.420s 4595.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.150s 8286.845us 1 1 100.00
adc_ctrl_tl_intg_err 15.900s 8608.189us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 15.900s 8608.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 0.990s 726.480us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 9 test runs
adc_ctrl_filters_polled 31231871178466774417592419431930657448622487851676184578128925705693489732282 394
UVM_INFO @ 345350775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 89995211084521165046882116828576905048719885222135288400719235459960441180191 394
UVM_INFO @ 336745848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 108068923078368972058223482132977199070253763777516336541710136127284236089514 394
UVM_INFO @ 517968329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 32566131134965277215079941732587044080767186639750373775129988610487027727078 394
UVM_INFO @ 342449274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 83187671149781971433006092089541644516172491257454582663200300100002298602217 394
UVM_INFO @ 405799173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 86493962039483262252374082149070566246442967832733718587380126052898784492127 394
UVM_INFO @ 382431810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 55393885941295241363433337149743656379877485746439827395561217466228881155876 394
UVM_INFO @ 443556716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 66872063351076048638672188615235336556204778476725667222074946485313784478939 394
UVM_INFO @ 372094025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 13494262079932352694199428190908702260683048882507328421566710728949912007714 395
UVM_INFO @ 726480245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---