Simulation Results: aes/masked

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.44 %
  • code
  • 93.60 %
  • assert
  • 98.23 %
  • func
  • 73.50 %
  • block
  • 94.24 %
  • line
  • 95.93 %
  • branch
  • 87.16 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 65.206us 1 1 100.00
smoke 1 1 100.00
aes_smoke 13.000s 1872.413us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 71.602us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 85.828us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 608.759us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 415.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 166.348us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 85.828us 1 1 100.00
aes_csr_aliasing 3.000s 415.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 13.000s 1872.413us 1 1 100.00
aes_config_error 2.000s 83.261us 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
key_length 3 3 100.00
aes_smoke 13.000s 1872.413us 1 1 100.00
aes_config_error 2.000s 83.261us 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 260.046us 1 1 100.00
aes_b2b 3.000s 117.630us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 13.000s 1872.413us 1 1 100.00
aes_config_error 2.000s 83.261us 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
aes_alert_reset 4.000s 224.639us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 71.596us 1 1 100.00
aes_config_error 2.000s 83.261us 1 1 100.00
aes_alert_reset 4.000s 224.639us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 119.117us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 321.095us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 224.639us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 260.046us 1 1 100.00
aes_sideload 7.000s 395.333us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 88.771us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 18.000s 4595.986us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 66.563us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 609.971us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 609.971us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 71.602us 1 1 100.00
aes_csr_rw 1.000s 85.828us 1 1 100.00
aes_csr_aliasing 3.000s 415.937us 1 1 100.00
aes_same_csr_outstanding 2.000s 152.306us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 71.602us 1 1 100.00
aes_csr_rw 1.000s 85.828us 1 1 100.00
aes_csr_aliasing 3.000s 415.937us 1 1 100.00
aes_same_csr_outstanding 2.000s 152.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 279.333us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 149.207us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1483.971us 1 1 100.00
aes_tl_intg_err 2.000s 179.234us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 179.234us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 224.639us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 13.000s 1872.413us 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
aes_alert_reset 4.000s 224.639us 1 1 100.00
aes_core_fi 3.000s 101.359us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 83.261us 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
aes_core_fi 3.000s 101.359us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 210.718us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 65.962us 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 260.046us 1 1 100.00
aes_sideload 7.000s 395.333us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.962us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.962us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 65.962us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 65.962us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 65.962us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 260.046us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 170.847us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
aes_ctr_fi 2.000s 98.718us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 170.847us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 170.847us 1 1 100.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 98.718us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 170.847us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
aes_ctr_fi 2.000s 98.718us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 224.639us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
aes_ctr_fi 2.000s 98.718us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
aes_ctr_fi 2.000s 98.718us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 98.718us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 4.000s 170.847us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 170.847us 1 1 100.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 67.823us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
aes_control_fi 70630106612083300590558293736421514050446699324872375120455113730688194861472 None
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 32084643626545754871501973278978572031746060964602159548342886253163597408413 174
UVM_INFO @ 67822561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---