Simulation Results: alert_handler

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.30 %
  • code
  • 91.69 %
  • assert
  • 96.37 %
  • func
  • 76.83 %
  • line
  • 99.66 %
  • branch
  • 98.02 %
  • cond
  • 91.32 %
  • toggle
  • 93.62 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 21.510s 605.301us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.740s 131.639us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.870s 63.776us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 64.980s 2920.807us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 128.840s 6976.650us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.400s 101.897us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.870s 63.776us 1 1 100.00
alert_handler_csr_aliasing 128.840s 6976.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 41.760s 4832.994us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 30.800s 850.695us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 595.130s 12170.732us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 5.720s 435.574us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 21.510s 605.301us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 17.520s 328.985us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 21.040s 3306.142us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 54.290s 2279.370us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 884.470s 76320.619us 1 1 100.00
alert_handler_lpg_stub_clk 817.170s 47357.552us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1266.780s 39891.924us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 6.840s 241.507us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.780s 14.126us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.280s 6.447us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.600s 184.142us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.600s 184.142us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.740s 131.639us 1 1 100.00
alert_handler_csr_rw 3.870s 63.776us 1 1 100.00
alert_handler_csr_aliasing 128.840s 6976.650us 1 1 100.00
alert_handler_same_csr_outstanding 20.410s 989.024us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.740s 131.639us 1 1 100.00
alert_handler_csr_rw 3.870s 63.776us 1 1 100.00
alert_handler_csr_aliasing 128.840s 6976.650us 1 1 100.00
alert_handler_same_csr_outstanding 20.410s 989.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 63.930s 2286.049us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 63.930s 2286.049us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 63.930s 2286.049us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 63.930s 2286.049us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 198.920s 4600.864us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
alert_handler_tl_intg_err 2.320s 37.465us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.320s 37.465us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 63.930s 2286.049us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 21.510s 605.301us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 21.510s 605.301us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 21.510s 605.301us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 21.510s 605.301us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.720s 435.574us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 884.470s 76320.619us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.720s 435.574us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 595.130s 12170.732us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 595.130s 12170.732us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.870s 431.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 137.230s 2001.058us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 73501588632130349954235153544049837383223481035728732599747576749868218625638 101
UVM_INFO @ 2279369881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---