Simulation Results: chip

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.23 %
  • code
  • 84.86 %
  • assert
  • 97.37 %
  • func
  • 37.45 %
  • line
  • 94.34 %
  • branch
  • 93.14 %
  • cond
  • 88.44 %
  • toggle
  • 91.23 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.70%
V2S
100.00%
V3
65.38%
unmapped
72.73%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 180.250s 2940.362us 1 1 100.00
chip_sw_example_rom 80.720s 2170.380us 1 1 100.00
chip_sw_example_manufacturer 144.570s 2772.243us 1 1 100.00
chip_sw_example_concurrency 141.480s 2326.456us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 327.300s 8142.444us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 206.080s 3887.366us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 464.210s 6211.127us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3847.940s 27356.992us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 51.520s 2353.770us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3847.940s 27356.992us 1 1 100.00
chip_csr_rw 206.080s 3887.366us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.980s 187.701us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 268.980s 3851.972us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 268.980s 3851.972us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 268.980s 3851.972us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 390.810s 4743.583us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 390.810s 4743.583us 1 1 100.00
chip_sw_uart_tx_rx_idx1 371.710s 4441.218us 1 1 100.00
chip_sw_uart_tx_rx_idx2 365.210s 3763.822us 1 1 100.00
chip_sw_uart_tx_rx_idx3 382.580s 4797.261us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1720.360s 13388.293us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 436.610s 4391.610us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 279.360s 4460.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 192.300s 4121.116us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 192.300s 4121.116us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 190.370s 3654.128us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 154.970s 3133.484us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 207.900s 4142.701us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 831.500s 13883.460us 1 1 100.00
chip_tap_straps_testunlock0 117.050s 2788.050us 1 1 100.00
chip_tap_straps_rma 91.000s 2987.394us 1 1 100.00
chip_tap_straps_prod 85.430s 2389.569us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 147.110s 2949.815us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 770.080s 9340.957us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 402.890s 5713.274us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 402.890s 5713.274us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 501.990s 8420.972us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1129.920s 12364.062us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 404.530s 4314.003us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 645.730s 5829.675us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3693.470s 18358.025us 1 1 100.00
chip_sw_aes_enc_jitter_en 175.920s 3600.568us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 732.750s 7305.813us 1 1 100.00
chip_sw_hmac_enc_jitter_en 171.320s 3300.506us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1522.660s 11932.284us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 195.430s 2891.422us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 361.800s 5071.613us 1 1 100.00
chip_sw_clkmgr_jitter 135.370s 3091.719us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 198.920s 2878.866us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 352.330s 6605.019us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 200.700s 4622.336us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 166.270s 2852.684us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 200.700s 4622.336us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 182.840s 2979.071us 1 1 100.00
chip_sw_aes_smoketest 192.440s 3749.210us 1 1 100.00
chip_sw_aon_timer_smoketest 179.650s 2623.808us 1 1 100.00
chip_sw_clkmgr_smoketest 129.880s 3204.809us 1 1 100.00
chip_sw_csrng_smoketest 174.580s 3007.910us 1 1 100.00
chip_sw_entropy_src_smoketest 788.610s 6769.003us 1 1 100.00
chip_sw_gpio_smoketest 157.480s 3683.893us 1 1 100.00
chip_sw_hmac_smoketest 198.800s 3077.128us 1 1 100.00
chip_sw_kmac_smoketest 183.810s 3037.905us 1 1 100.00
chip_sw_otbn_smoketest 1319.500s 9756.744us 1 1 100.00
chip_sw_pwrmgr_smoketest 268.410s 6197.850us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 225.820s 5957.405us 1 1 100.00
chip_sw_rv_plic_smoketest 159.920s 2632.488us 1 1 100.00
chip_sw_rv_timer_smoketest 139.490s 3476.364us 1 1 100.00
chip_sw_rstmgr_smoketest 127.750s 3285.285us 1 1 100.00
chip_sw_sram_ctrl_smoketest 160.570s 3094.125us 1 1 100.00
chip_sw_uart_smoketest 181.370s 2734.106us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 148.890s 3596.615us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 374.340s 4510.909us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7973.010s 62748.070us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3100.780s 14581.009us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 267.389s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 215.410s 3952.349us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 186.120s 3599.294us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7127.740s 55785.885us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7497.110s 58902.557us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 128.540s 2963.032us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 128.540s 2963.032us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3847.940s 27356.992us 1 1 100.00
chip_same_csr_outstanding 1136.260s 14782.976us 1 1 100.00
chip_csr_hw_reset 327.300s 8142.444us 1 1 100.00
chip_csr_rw 206.080s 3887.366us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3847.940s 27356.992us 1 1 100.00
chip_same_csr_outstanding 1136.260s 14782.976us 1 1 100.00
chip_csr_hw_reset 327.300s 8142.444us 1 1 100.00
chip_csr_rw 206.080s 3887.366us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 24.900s 950.802us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 7.110s 44.376us 1 1 100.00
xbar_smoke_large_delays 48.400s 7508.297us 1 1 100.00
xbar_smoke_slow_rsp 37.030s 3702.986us 1 1 100.00
xbar_random_zero_delays 21.780s 313.751us 1 1 100.00
xbar_random_large_delays 172.240s 29382.599us 1 1 100.00
xbar_random_slow_rsp 64.100s 6729.105us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 28.040s 860.470us 1 1 100.00
xbar_error_and_unmapped_addr 35.340s 1258.798us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 61.820s 2475.664us 1 1 100.00
xbar_error_and_unmapped_addr 35.340s 1258.798us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 53.490s 1616.593us 1 1 100.00
xbar_access_same_device_slow_rsp 305.630s 33934.329us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 23.370s 357.857us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 45.670s 1702.640us 1 1 100.00
xbar_stress_all_with_error 152.800s 6569.148us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 26.990s 144.397us 1 1 100.00
xbar_stress_all_with_reset_error 218.200s 3901.716us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3100.780s 14581.009us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2656.990s 37170.174us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3091.370s 15840.750us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 91.952s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 61.058s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 112.705s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 106.787s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 72.545s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 92.301s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 8.329s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 71.985s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 8.295s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 76.396s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 232.190s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 121.538s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 135.433s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 83.578s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 183.411s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.890s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 19.880s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.430s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.140s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 17.180s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.260s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.080s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.060s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.630s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.630s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.030s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.190s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.480s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.500s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 15.960s 10.380us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 92.986s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 77.328s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 71.175s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 161.713s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 118.863s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 3178.610s 15798.719us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 3082.310s 16498.145us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3048.150s 16444.259us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3257.320s 16713.427us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2804.020s 34764.634us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2804.020s 34764.634us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 167.310s 3508.346us 1 1 100.00
chip_sw_aes_enc_jitter_en 175.920s 3600.568us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 146.770s 2677.856us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 149.070s 2276.269us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 725.080s 8613.015us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 193.330s 3590.489us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 336.260s 5105.297us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 618.790s 5197.834us 1 1 100.00
chip_plic_all_irqs_10 363.490s 4168.780us 1 1 100.00
chip_plic_all_irqs_20 431.620s 4466.739us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 214.330s 3173.707us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1207.050s 15940.026us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 285.470s 4110.499us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 123.070s 2310.403us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.144s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 774.260s 6455.846us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1067.470s 8367.909us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 788.730s 8319.830us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8978.760s 254612.502us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 211.490s 3862.623us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 268.410s 6197.850us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 211.490s 3862.623us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 530.570s 7833.312us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 530.570s 7833.312us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 338.910s 7430.655us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 408.240s 5619.874us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 528.880s 6177.295us 1 1 100.00
chip_sw_aes_idle 149.070s 2276.269us 1 1 100.00
chip_sw_hmac_enc_idle 184.820s 3222.519us 1 1 100.00
chip_sw_kmac_idle 154.860s 2299.982us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 365.160s 5303.902us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 305.740s 4668.440us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 258.170s 3875.926us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 388.680s 5368.949us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 926.910s 11933.074us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 418.500s 4098.252us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 406.260s 5454.338us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 452.990s 4834.954us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 374.560s 4144.339us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 395.830s 4339.613us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 394.400s 4731.124us 1 1 100.00
chip_sw_ast_clk_outputs 501.990s 8420.972us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 317.120s 5990.833us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 452.990s 4834.954us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 374.560s 4144.339us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 404.530s 4314.003us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 645.730s 5829.675us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3693.470s 18358.025us 1 1 100.00
chip_sw_aes_enc_jitter_en 175.920s 3600.568us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 732.750s 7305.813us 1 1 100.00
chip_sw_hmac_enc_jitter_en 171.320s 3300.506us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1522.660s 11932.284us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 195.430s 2891.422us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 361.800s 5071.613us 1 1 100.00
chip_sw_clkmgr_jitter 135.370s 3091.719us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 133.840s 3240.638us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 360.780s 5399.836us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 655.030s 7282.032us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3994.970s 25301.591us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 144.830s 2684.568us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 165.870s 3432.871us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 785.590s 9543.726us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 174.950s 3185.137us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 381.270s 5959.985us 1 1 100.00
chip_sw_flash_init_reduced_freq 992.760s 21178.920us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2333.900s 17847.449us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 501.990s 8420.972us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 376.790s 4899.314us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 285.760s 3669.898us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 774.260s 6455.846us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1995.710s 24298.816us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 279.160s 4479.999us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 574.760s 7731.190us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 159.280s 3196.772us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2323.060s 15097.224us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 130.430s 2920.173us 1 1 100.00
chip_sw_edn_entropy_reqs 614.130s 5548.874us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 130.430s 2920.173us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1995.710s 24298.816us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 126.730s 2892.879us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1106.550s 22661.470us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 630.370s 5632.665us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 645.730s 5829.675us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 371.320s 4376.533us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 404.530s 4314.003us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3619.920s 44400.138us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1106.550s 22661.470us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 207.910s 3843.207us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1277.820s 10889.033us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.210s 3162.892us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3619.920s 44400.138us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.210s 3162.892us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.210s 3162.892us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.210s 3162.892us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.210s 3162.892us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 293.850s 9434.697us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 511.940s 5677.643us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 443.540s 6148.981us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 443.540s 6148.981us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 138.940s 2732.953us 1 1 100.00
chip_sw_hmac_enc_jitter_en 171.320s 3300.506us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 184.820s 3222.519us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 784.400s 6969.423us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 647.190s 5820.617us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 365.660s 5215.545us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 412.090s 5803.744us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 430.470s 5585.935us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 267.630s 3647.797us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1277.820s 10889.033us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1522.660s 11932.284us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 982.150s 8681.112us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 725.080s 8613.015us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 1904.670s 11194.284us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 183.950s 3494.465us 1 1 100.00
chip_sw_kmac_mode_kmac 231.510s 3699.567us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 195.430s 2891.422us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1277.820s 10889.033us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 132.730s 2138.216us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 526.900s 5524.809us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 154.860s 2299.982us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 336.260s 5105.297us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 831.500s 13883.460us 1 1 100.00
chip_tap_straps_rma 91.000s 2987.394us 1 1 100.00
chip_tap_straps_prod 85.430s 2389.569us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 154.180s 2962.728us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 821.750s 7496.238us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 133.210s 3162.892us 0 1 0.00
chip_sw_flash_rma_unlocked 3619.920s 44400.138us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 197.420s 3442.388us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 492.000s 7981.006us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 455.650s 7180.720us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 471.910s 7299.183us 0 1 0.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_keymgr_key_derivation 1277.820s 10889.033us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 316.210s 8883.938us 1 1 100.00
chip_sw_sram_ctrl_execution_main 568.020s 8741.955us 1 1 100.00
chip_prim_tl_access 293.850s 9434.697us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 317.120s 5990.833us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 418.500s 4098.252us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 406.260s 5454.338us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 452.990s 4834.954us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 374.560s 4144.339us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 395.830s 4339.613us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 394.400s 4731.124us 1 1 100.00
chip_tap_straps_dev 831.500s 13883.460us 1 1 100.00
chip_tap_straps_rma 91.000s 2987.394us 1 1 100.00
chip_tap_straps_prod 85.430s 2389.569us 1 1 100.00
chip_rv_dm_lc_disabled 342.160s 12600.055us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 134.650s 3571.390us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 69.040s 3334.622us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 92.180s 3378.137us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 124.440s 3489.838us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1180.930s 22528.675us 1 1 100.00
chip_rv_dm_lc_disabled 342.160s 12600.055us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 646.690s 10183.157us 0 1 0.00
chip_sw_lc_walkthrough_prod 656.320s 9048.880us 0 1 0.00
chip_sw_lc_walkthrough_prodend 472.580s 8473.393us 1 1 100.00
chip_sw_lc_walkthrough_rma 387.430s 5915.474us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1180.930s 22528.675us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 77.970s 2746.223us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 68.890s 2516.401us 1 1 100.00
rom_volatile_raw_unlock 90.519s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3785.200s 17507.783us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3693.470s 18358.025us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 528.880s 6177.295us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 528.880s 6177.295us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 528.880s 6177.295us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 259.760s 3558.301us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1106.550s 22661.470us 1 1 100.00
chip_sw_otbn_mem_scramble 259.760s 3558.301us 1 1 100.00
chip_sw_keymgr_key_derivation 1277.820s 10889.033us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 358.610s 4806.274us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.090s 3320.774us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1106.550s 22661.470us 1 1 100.00
chip_sw_otbn_mem_scramble 259.760s 3558.301us 1 1 100.00
chip_sw_keymgr_key_derivation 1277.820s 10889.033us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 358.610s 4806.274us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.090s 3320.774us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 345.920s 5938.021us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 154.180s 2962.728us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 197.420s 3442.388us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 492.000s 7981.006us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 455.650s 7180.720us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 471.910s 7299.183us 0 1 0.00
chip_sw_lc_ctrl_transition 559.690s 13243.476us 1 1 100.00
chip_prim_tl_access 293.850s 9434.697us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 293.850s 9434.697us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 922.340s 8634.013us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 214.990s 7373.223us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1010.310s 27354.151us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 202.760s 7478.729us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 322.870s 8166.213us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 326.720s 7267.249us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 958.000s 23202.980us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 907.290s 14462.505us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 530.570s 7833.312us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 883.850s 12121.158us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 316.230s 4433.872us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 214.990s 7373.223us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 209.480s 4092.176us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 729.950s 13607.592us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 220.390s 8265.082us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 113.890s 2874.884us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 537.950s 13855.266us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 672.160s 8295.760us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 916.620s 12060.322us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1791.320s 28952.297us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 198.180s 3875.891us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 316.210s 8883.938us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 316.210s 8883.938us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 916.620s 12060.322us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 537.950s 13855.266us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 316.230s 4433.872us 1 1 100.00
chip_sw_pwrmgr_smoketest 268.410s 6197.850us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 289.940s 4186.209us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 361.630s 6141.585us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 211.410s 4202.819us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1207.050s 15940.026us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 158.830s 3430.912us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1067.470s 8367.909us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 412.450s 5413.407us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 505.010s 4732.867us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 130.040s 2831.554us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.090s 3320.774us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 361.630s 6141.585us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 361.630s 6141.585us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 835.120s 12714.018us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 864.370s 13555.042us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 289.940s 4186.209us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 190.300s 3332.137us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 319.470s 7391.720us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 91.000s 2987.394us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 342.160s 12600.055us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 618.790s 5197.834us 1 1 100.00
chip_plic_all_irqs_10 363.490s 4168.780us 1 1 100.00
chip_plic_all_irqs_20 431.620s 4466.739us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 166.550s 3506.205us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 124.580s 2472.990us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3100.780s 14581.009us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 472.230s 7914.093us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 238.020s 4019.098us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 228.710s 4294.948us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 194.500s 2995.206us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 358.610s 4806.274us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 361.800s 5071.613us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 425.630s 8969.379us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 513.690s 9828.911us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 568.020s 8741.955us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
chip_sw_data_integrity_escalation 402.890s 5713.274us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 672.160s 8295.760us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1007.930s 22046.856us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 161.890s 3092.175us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 230.180s 4413.788us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 340.630s 4336.918us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1007.930s 22046.856us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1007.930s 22046.856us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2538.790s 19955.076us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2538.790s 19955.076us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 290.840s 6132.048us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2804.020s 34764.634us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 120.730s 3411.629us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 181.060s 3309.392us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 266.760s 4072.183us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 320.050s 3659.676us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 961.720s 7920.326us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5172.900s 31752.504us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1717.690s 12124.606us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 173.160s 3148.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 182.000s 2949.842us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 82.520s 2316.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9990.890s 71435.691us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1133.120s 6939.637us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 195.600s 4294.902us 0 1 0.00
rom_e2e_jtag_debug_dev 191.400s 4908.541us 0 1 0.00
rom_e2e_jtag_debug_rma 194.340s 5006.342us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 61.060s 2152.695us 0 1 0.00
rom_e2e_jtag_inject_dev 92.950s 3131.070us 0 1 0.00
rom_e2e_jtag_inject_rma 46.480s 2314.232us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 162.000s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 255.790s 3701.884us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 346.380s 3011.392us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 873.060s 5372.172us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1035.430s 8605.023us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 251.600s 2841.435us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 593.560s 5387.543us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 120.270s 2734.695us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 146.230s 3068.976us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 254.990s 6185.755us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 311.160s 5837.503us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 916.620s 12060.322us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 195.600s 4294.902us 0 1 0.00
rom_e2e_jtag_debug_dev 191.400s 4908.541us 0 1 0.00
rom_e2e_jtag_debug_rma 194.340s 5006.342us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 325.570s 4868.996us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 459.120s 5345.549us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5686.380s 39030.907us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5686.380s 39030.907us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 155.040s 3565.255us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 390.810s 4743.583us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3001.910s 18723.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 11 72.73
chip_sival_flash_info_access 197.860s 3326.586us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 438.930s 6031.366us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.600s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 157.680s 3293.283us 1 1 100.00
chip_sw_otp_ctrl_descrambling 184.480s 3105.870us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 212.430s 3586.990us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.244s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 188.610s 3030.973us 1 1 100.00
ate_bootstrap_flash_erase 622.040s 10010.120us 0 1 0.00
ate_bootstrap_one_frame 6329.520s 45525.019us 1 1 100.00
ate_bootstrap_disjoint 9956.090s 85059.225us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 86950880555968225456951046079155936281220049667613402503240987443573695624640 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 45952396496342321369873913176550882813512564611268861138032089078723526298097 None
---- STDERR ----
Another command (pid=345488) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=360562) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 102621966865092554152078114249558254419911179696388362664230956943956845745381 None
---- STDERR ----
Another command (pid=457518) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=471017) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 96663252751000911689156947282468907548849192811851853189373826255013334947710 None
Another command (pid=615020) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=645605) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=591534) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 76516935148644944038850137562931347301484259697254314502520457399277877975101 None
Another command (pid=639735) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=622625) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=603515) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 67530444007144792107234534192019779281466778791745243498829488027183692217285 None
Another command (pid=467487) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=576616) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=566761) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 54713432757801294152061404112836764111678147948001947125337559965146757676243 None
---- STDERR ----
Another command (pid=345488) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=360562) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 15028862601860750255188384536969727933495229251695856138563802491329728337984 None
---- STDERR ----
Another command (pid=346896) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 85631550488698330337005340736018562817629413361728816023992338813877809450931 None
Another command (pid=351076) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=560723) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=561383) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 80181346820207405610790207898571176974907208229490283235913949212948841480474 None
---- STDERR ----
Another command (pid=346896) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 47152214061071554454489969376941358192153855407243653307084916697787744044028 None
Another command (pid=365084) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=558703) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=352311) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 66427661827771326097623791736490348750431253683171328791904410150340590009300 None
Another command (pid=687473) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=713609) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=706607) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 4289372852041281625023295182509757545310739145955433180185524348399078262956 None
Another command (pid=557233) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=471747) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=559926) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 52338044936228480199725267843187567291437205123596096343722337318279573580681 None
Another command (pid=603515) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=487646) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=654780) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 45190598724046409039829411626345167137903624145714397897317732140551400734161 None
Another command (pid=472906) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=471747) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=567699) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 1867219699525371422711688393817140713408439114287771835626325155247200303629 None
Another command (pid=783558) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=669641) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=798361) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 20041120224044310190397580556812743600451012962993750688100924800287059901851 None
---- STDERR ----
Another command (pid=345488) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=360562) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 86675746358887117442730173177029829715292623457228096306395251763083617708592 None
Another command (pid=349487) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=346896) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=451671) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 73154494057206935247121312146208888269431366119655309894920967854126797506296 None
Another command (pid=350421) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=353122) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=346896) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 104912209505969180439222977494191547773456584356686540782765700784729586322435 None
Another command (pid=594679) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=629772) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=577278) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 38806895276895998989042882707614286236899192441214801595231108509411558746366 None
Another command (pid=377447) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=457518) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=471017) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 18397602513193352710636934858426387456225296420698989965151549873263294593401 None
Another command (pid=345488) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=360562) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=350421) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 85640631947138377996042746282308970248441904343541762322284071182620256942588 None
Another command (pid=631152) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=800848) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=806258) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 16592527261788945177936943523812438220402325771132276454606139789083303198513 None
Another command (pid=471017) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=352458) is running. Waiting for it to complete on the server (server_pid=240539)...
Another command (pid=457050) is running. Waiting for it to complete on the server (server_pid=240539)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 73516429735247660120235670371265373811815441600108942287987220793980172113914 332
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 43164576575138040638319952257027992413481757107609830782073255459139540564392 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 30544521412943773565537777492655691101578600675659788399864111084371368068502 324
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 26115117890526189582027571422932546166654344139838559686027168621123705752132 324
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 77935869650347950430029473616866760232985773945281406047801561660167943458938 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 19080573664796025619519669874339416507649431831321749442444786411980747732058 312
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 51675208020782141786973266977986239364080028059218636516840918101829173113371 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 105674682889885823355908595048665854981731363284725389050098633086745129160513 371
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 71113583088024406559553024220944877254442997848142215970394446460485633533166 370
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 81592187518428332577648518280724844436996220723705649542663333711212684547779 373
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 93380252545740670867715968986107133662561943522269913358671835075426706758218 333
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 8055528808344673243909709274925579396470206858173437391612484200643066244760 333
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 97560801218486910404737993067444444107647780470006615601773663465272449297327 333
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 36208684324582376271778869340720396910354907098225210740020579734372460362085 369
UVM_INFO @ 10183.157440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 7341847724846151671760370028289898008186411786872524470874611538549756096739 369
UVM_INFO @ 9048.880034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 5203044109208384473003360697053436093715245526665394716164875459072926989875 341
UVM_INFO @ 5915.474404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 59282912515138771017636973198104034054421679156071661093547181483980385316885 332
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 75693555807362100917638122431715003138734494034483868733722765981239207928004 331
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 37735210648729235401406709394321577580981125400845140160703294169386317523376 333
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 2 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 86755397439382881971014040789154015155722281299625789663660433951215620711712 344
UVM_ERROR @ 13855.266500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13855.266500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 106499158605448816225172710347956390555796932363573339100939508165245897688617 330
UVM_ERROR @ 8166.213000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8166.213000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 9930469784834115409617598472849430921757642937357095428892572156918166143020 318
UVM_ERROR @ 2874.883810 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2874.883810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 15337806097699875203666138109126847985716808432433654295009407839604649668852 356
UVM_ERROR @ 13607.591687 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 13607.591687 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 113017363255827770023692243668562471896147636128354176711844666941779649396682 218
TL item was: req: (cip_tl_seq_item@136442) { a_addr: 'h10708 a_data: 'he9ec6230 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h18d28 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2963.031536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 79816244623487879976357566991355827383501079365603339049305659563599439184854 224
TL item was: req: (cip_tl_seq_item@32040) { a_addr: 'h1047c a_data: 'h9a6ea1c9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1990d d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2353.770144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 80809464209499966758938073693275824339755888846218136150493733568226105848597 367
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 62304730083143153279242350586897650794314899241696904499291890815493670476449 325
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 86264079788916372000269664040789675051218405114919728287311470014338987599351 373
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 12626767998293914978066270259539885665733551591102721443385754000417452532605 331
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 115440679462543767106112311265936383425567383462717957842519811956502594846641 456
UVM_INFO @ 3654.128500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 75968823355016538054032473335549764577120040189953913937177360472413010204412 325
UVM_INFO @ 4019.098200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 22393935063358355691097593835274145781481747529137986718308724935609386814512 309
UVM_INFO @ 3162.891977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 46453069302472914435845997096933448917539238593409236907864643942133905807255 347
UVM_INFO @ 7299.183096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 55794184942414382460017967720645995610581889546641584411073461549711260676008 321
UVM_ERROR @ 3068.976180 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3068.976180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 80541960405430315168161264038780206480627669376652176134741135187475004300195 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 61898970994444262594228299888162198260978142452923303267033565211388049851377 325
UVM_ERROR @ 7373.223195 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 7373.223195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 59997123463987745166736530961196639750465578976597628090329366272883500395148 332
UVM_INFO @ 34764.633827 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 68805466078819224376141146946588543600866832387824611333681743500407297368159 307
UVM_INFO @ 3590.488610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 109177908580060806420349551639016031675306677048568691791979815675326918299419 308
UVM_INFO @ 2310.403036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 93881144355837059985648558800374445473428376816569949723799083251544088190977 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 2641906955284728546314540984684375756025999539341517256700539128892746740412 343
UVM_INFO @ 3701.883751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 34136822000699319606475757044063495109508089179769144037127180148182708691989 317
UVM_INFO @ 3952.349000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 23586486648882467848927403408950059734824314073114954301675890842981868588005 323
UVM_INFO @ 3599.294000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 36909901037984503780384751472750341057037917867098010633173605251328728090855 327
UVM_INFO @ 12364.061994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 71123390575295673403270686563733339536791096646449547564195318491228435372816 277
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 69382496208932327243812992838451296526458381738274320576038098165110532132516 330
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 106564247420653474110338562300208851248041027161080364644912517744394131820530 333
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 38175200542041928268444845748473515113206957215676175402975366504070928012561 324
UVM_INFO @ 15798.719430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 92016024111219227578320631963313029256853202822580888273906432469983423879284 324
UVM_INFO @ 16498.145404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 109832521134779051394726955315355936632246912971915135989997112273644232897208 324
UVM_INFO @ 16444.259464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 34910696725528234005152108281820898660980614995892488558326752832861750217726 327
UVM_ERROR @ 4510.908952 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4510.908952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---