Simulation Results: clkmgr

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.00 %
  • code
  • 97.48 %
  • assert
  • 93.79 %
  • func
  • 84.73 %
  • line
  • 98.21 %
  • branch
  • 98.17 %
  • cond
  • 91.83 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.860s 74.005us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.060s 57.349us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.720s 689.833us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.400s 40.841us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.590s 109.949us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
clkmgr_csr_aliasing 1.400s 40.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 16.100us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.000s 109.026us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.870s 33.606us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.100s 54.009us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.860s 74.005us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.880s 2092.305us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.300s 134.416us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.880s 2092.305us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 9.020s 3550.330us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.090s 44.374us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.750s 37.277us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.750s 37.277us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.060s 57.349us 1 1 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
clkmgr_csr_aliasing 1.400s 40.841us 1 1 100.00
clkmgr_same_csr_outstanding 1.710s 240.251us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.060s 57.349us 1 1 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
clkmgr_csr_aliasing 1.400s 40.841us 1 1 100.00
clkmgr_same_csr_outstanding 1.710s 240.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.770s 2.166us 0 1 0.00
clkmgr_tl_intg_err 2.900s 787.513us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 182.968us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 182.968us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 182.968us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 182.968us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 355.760s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.900s 787.513us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.880s 2092.305us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.300s 134.416us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.570s 182.968us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.060s 108.743us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 87.971us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.020s 43.404us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.140s 25.566us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.380s 92.667us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.770s 2.166us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 17.743us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.770s 2.166us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.810s 1109.008us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 44.650s 3884.242us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 16678755580249509939548229781080735999654394718449729492614481346938032857763 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 103800161905001614309753256574823425731988492081282440367972059521461792976722 78
UVM_INFO @ 2166219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---