Simulation Results: csrng

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.50 %
  • code
  • 92.08 %
  • assert
  • 93.01 %
  • func
  • 65.42 %
  • block
  • 96.75 %
  • line
  • 97.41 %
  • branch
  • 91.83 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 15.000s 17.503us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 29.000s 29.400us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 29.000s 15.964us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 78.000s 5674.672us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 30.000s 31.752us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 30.000s 96.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 29.000s 15.964us 1 1 100.00
csrng_csr_aliasing 30.000s 31.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
alerts 1 1 100.00
csrng_alert 33.000s 120.547us 1 1 100.00
err 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 30.000s 42.413us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 30.000s 42.413us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 26.000s 1329.182us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 21.000s 15.380us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 29.000s 15.016us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 74.624us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 74.624us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 29.000s 29.400us 1 1 100.00
csrng_csr_rw 29.000s 15.964us 1 1 100.00
csrng_csr_aliasing 30.000s 31.752us 1 1 100.00
csrng_same_csr_outstanding 21.000s 58.598us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 29.000s 29.400us 1 1 100.00
csrng_csr_rw 29.000s 15.964us 1 1 100.00
csrng_csr_aliasing 30.000s 31.752us 1 1 100.00
csrng_same_csr_outstanding 21.000s 58.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
csrng_tl_intg_err 3.000s 162.173us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 22.000s 41.517us 1 1 100.00
csrng_csr_rw 29.000s 15.964us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 33.000s 120.547us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 26.000s 1329.182us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 33.000s 120.547us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 26.000s 1329.182us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 33.000s 120.547us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 162.173us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
csrng_sec_cm 17.000s 250.826us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 26.000s 110.767us 1 1 100.00
csrng_err 30.000s 24.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.088s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 100030788749523776633082320220537430801493410392734017049215247744522856886145 130
UVM_INFO @ 42412681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 86584785833462010606952156985833480935328918810815146260450815670346765375429 None