Simulation Results: edn/edn0

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.73 %
  • code
  • 80.67 %
  • assert
  • 94.14 %
  • func
  • 79.37 %
  • line
  • 97.23 %
  • branch
  • 90.79 %
  • cond
  • 85.26 %
  • toggle
  • 80.62 %
  • FSM
  • 49.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 50.666us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 43.708us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 50.363us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.540s 232.033us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 31.241us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.510s 58.624us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 50.363us 1 1 100.00
edn_csr_aliasing 1.200s 31.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.080s 107.313us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.080s 107.313us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.080s 107.313us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 38.297us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.120s 24.646us 1 1 100.00
errs 1 1 100.00
edn_err 1.030s 20.204us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 34.803us 1 1 100.00
edn_disable_auto_req_mode 1.320s 52.576us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.550s 168.931us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 13.241us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.060s 54.412us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.550s 256.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.550s 256.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 43.708us 1 1 100.00
edn_csr_rw 0.810s 50.363us 1 1 100.00
edn_csr_aliasing 1.200s 31.241us 1 1 100.00
edn_same_csr_outstanding 0.930s 16.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 43.708us 1 1 100.00
edn_csr_rw 0.810s 50.363us 1 1 100.00
edn_csr_aliasing 1.200s 31.241us 1 1 100.00
edn_same_csr_outstanding 0.930s 16.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.690s 402.812us 1 1 100.00
edn_tl_intg_err 2.080s 80.449us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 192.705us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.120s 24.646us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.690s 402.812us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.690s 402.812us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.690s 402.812us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.690s 402.812us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.120s 24.646us 1 1 100.00
edn_sec_cm 4.690s 402.812us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.120s 24.646us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.080s 80.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.090s 5382.459us 1 1 100.00