Simulation Results: edn/edn1

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.12 %
  • code
  • 84.38 %
  • assert
  • 97.14 %
  • func
  • 79.83 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 90.08 %
  • toggle
  • 95.51 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 44.986us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 27.453us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 18.316us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.800s 877.710us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 17.373us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.110s 30.149us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 18.316us 1 1 100.00
edn_csr_aliasing 1.000s 17.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.210s 42.511us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.210s 42.511us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.210s 42.511us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.750s 31.207us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 180.222us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 72.562us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 34.012us 1 1 100.00
edn_disable_auto_req_mode 0.930s 92.729us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.460s 286.339us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.810s 230.133us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 19.328us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.440s 118.317us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.440s 118.317us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 27.453us 1 1 100.00
edn_csr_rw 0.800s 18.316us 1 1 100.00
edn_csr_aliasing 1.000s 17.373us 1 1 100.00
edn_same_csr_outstanding 0.900s 28.634us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 27.453us 1 1 100.00
edn_csr_rw 0.800s 18.316us 1 1 100.00
edn_csr_aliasing 1.000s 17.373us 1 1 100.00
edn_same_csr_outstanding 0.900s 28.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.710s 344.335us 1 1 100.00
edn_tl_intg_err 1.350s 61.457us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 31.016us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 180.222us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.710s 344.335us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.710s 344.335us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.710s 344.335us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.710s 344.335us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 180.222us 1 1 100.00
edn_sec_cm 3.710s 344.335us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 180.222us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.350s 61.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 14.280s 2081.848us 1 1 100.00