Simulation Results: flash_ctrl

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.06 %
  • code
  • 94.16 %
  • assert
  • 89.42 %
  • func
  • 95.60 %
  • line
  • 95.95 %
  • branch
  • 97.12 %
  • cond
  • 93.11 %
  • toggle
  • 97.54 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.28%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 44.390s 29.007us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.040s 17.846us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 18.290s 44.304us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 20.650s 435.417us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 40.120s 5053.343us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.000s 160.979us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
flash_ctrl_csr_aliasing 40.120s 5053.343us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.360s 54.511us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.090s 162.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 15.950s 106.567us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 10.800s 125.219us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1379.160s 141505.486us 1 1 100.00
flash_ctrl_hw_rma_reset 558.150s 160185.206us 1 1 100.00
flash_ctrl_lcmgr_intg 5.840s 23.021us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1128.470s 307389.921us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 128.430s 2965.557us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.940s 41.702us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2962.090s 48916.439us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 45.930s 744.416us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.160s 44.598us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.530s 33.627us 1 1 100.00
flash_ctrl_re_evict 16.360s 119.424us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 39.950s 154.720us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 39.950s 154.720us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 261.130s 45811.250us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.090s 1247.268us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 266.400s 1657.697us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 303.660s 17765.763us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 366.880s 1920.589us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 722.930s 5621.590us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.650s 37.642us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 160.350s 2071.204us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.420s 21.665us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.650s 28.367us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 51.770s 46.067us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 51.330s 24195.590us 1 1 100.00
flash_ctrl_otp_reset 50.350s 183.056us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1379.160s 141505.486us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 80.230s 6277.487us 1 1 100.00
flash_ctrl_intr_wr 55.720s 3680.282us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 198.220s 50844.890us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 201.690s 109892.795us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 37.030s 6158.454us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 30.680s 826.742us 1 1 100.00
double_bit_err 4 5 80.00
flash_ctrl_read_word_sweep_derr 11.300s 29.320us 1 1 100.00
flash_ctrl_ro_derr 93.620s 10315.859us 1 1 100.00
flash_ctrl_rw_derr 142.550s 3519.782us 1 1 100.00
flash_ctrl_derr_detect 95.700s 1357.571us 1 1 100.00
flash_ctrl_integrity 288.120s 3871.484us 0 1 0.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 14.630s 167.126us 1 1 100.00
flash_ctrl_ro_serr 80.320s 1074.961us 1 1 100.00
flash_ctrl_rw_serr 141.220s 3084.613us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 31.960s 1852.655us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 46.360s 1157.055us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 112.400s 2154.148us 1 1 100.00
flash_ctrl_write_word_sweep 5.870s 118.925us 1 1 100.00
flash_ctrl_read_word_sweep 6.060s 24.522us 1 1 100.00
flash_ctrl_ro 77.620s 1322.036us 1 1 100.00
flash_ctrl_rw 401.110s 13676.128us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.740s 384.548us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 610.250s 173130.319us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 173.610s 10020.441us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.630s 233.611us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.330s 58.377us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.160s 456.434us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.160s 456.434us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.290s 44.304us 1 1 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
flash_ctrl_csr_aliasing 40.120s 5053.343us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.550s 607.001us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 18.290s 44.304us 1 1 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
flash_ctrl_csr_aliasing 40.120s 5053.343us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.550s 607.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 21.770s 261.918us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
flash_ctrl_tl_intg_err 180.450s 1159.745us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 180.450s 1159.745us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 180.450s 1159.745us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.060s 65.378us 1 1 100.00
flash_ctrl_wr_intg 5.900s 276.851us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 44.390s 29.007us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 50.350s 183.056us 1 1 100.00
flash_ctrl_disable 8.420s 21.665us 1 1 100.00
flash_ctrl_sec_info_access 44.900s 9488.882us 1 1 100.00
flash_ctrl_connect 6.650s 28.367us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.690s 75.948us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.620s 90.692us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.980s 63.982us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.420s 21.665us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.060s 65.378us 1 1 100.00
flash_ctrl_access_after_disable 5.660s 75.271us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 11.230s 39.030us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.420s 21.665us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.090s 1247.268us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 401.110s 13676.128us 1 1 100.00
sec_cm_mem_integrity 2 3 66.67
flash_ctrl_rw_serr 141.220s 3084.613us 1 1 100.00
flash_ctrl_rw_derr 142.550s 3519.782us 1 1 100.00
flash_ctrl_integrity 288.120s 3871.484us 0 1 0.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1379.160s 141505.486us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.660s 662.606us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.020s 96.324us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 10.270s 27.772us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1535.410s 1519.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 24.790s 121.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 54.740s 2558.255us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:290) m_otf_scb [process_read] unexpected double bit error * 1 test run
flash_ctrl_integrity 69252961221475408928844360874629805515992913122016663200728001285231173239206 108
UVM_INFO @ 3871483.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---