Simulation Results: hmac

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.47 %
  • code
  • 97.80 %
  • assert
  • 96.70 %
  • func
  • 43.91 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.95 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.570s 333.930us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.820s 66.468us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.730s 22.711us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.350s 735.472us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.600s 196.636us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.420s 22.359us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.730s 22.711us 1 1 100.00
hmac_csr_aliasing 2.600s 196.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 31.350s 1513.595us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 40.220s 4386.132us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 179.710s 19009.334us 1 1 100.00
hmac_test_sha384_vectors 347.650s 14677.604us 1 1 100.00
hmac_test_sha512_vectors 23.890s 1132.733us 1 1 100.00
hmac_test_hmac256_vectors 9.440s 323.119us 1 1 100.00
hmac_test_hmac384_vectors 8.060s 489.121us 1 1 100.00
hmac_test_hmac512_vectors 10.840s 330.712us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.840s 4052.939us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 328.480s 2241.090us 1 1 100.00
error 1 1 100.00
hmac_error 61.170s 6129.386us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 48.810s 5723.726us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.570s 333.930us 1 1 100.00
hmac_long_msg 31.350s 1513.595us 1 1 100.00
hmac_back_pressure 40.220s 4386.132us 1 1 100.00
hmac_datapath_stress 328.480s 2241.090us 1 1 100.00
hmac_burst_wr 18.840s 4052.939us 1 1 100.00
hmac_stress_all 298.400s 320790.379us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.570s 333.930us 1 1 100.00
hmac_long_msg 31.350s 1513.595us 1 1 100.00
hmac_back_pressure 40.220s 4386.132us 1 1 100.00
hmac_datapath_stress 328.480s 2241.090us 1 1 100.00
hmac_wipe_secret 48.810s 5723.726us 1 1 100.00
hmac_test_sha256_vectors 179.710s 19009.334us 1 1 100.00
hmac_test_sha384_vectors 347.650s 14677.604us 1 1 100.00
hmac_test_sha512_vectors 23.890s 1132.733us 1 1 100.00
hmac_test_hmac256_vectors 9.440s 323.119us 1 1 100.00
hmac_test_hmac384_vectors 8.060s 489.121us 1 1 100.00
hmac_test_hmac512_vectors 10.840s 330.712us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.570s 333.930us 1 1 100.00
hmac_long_msg 31.350s 1513.595us 1 1 100.00
hmac_back_pressure 40.220s 4386.132us 1 1 100.00
hmac_datapath_stress 328.480s 2241.090us 1 1 100.00
hmac_burst_wr 18.840s 4052.939us 1 1 100.00
hmac_error 61.170s 6129.386us 1 1 100.00
hmac_wipe_secret 48.810s 5723.726us 1 1 100.00
hmac_test_sha256_vectors 179.710s 19009.334us 1 1 100.00
hmac_test_sha384_vectors 347.650s 14677.604us 1 1 100.00
hmac_test_sha512_vectors 23.890s 1132.733us 1 1 100.00
hmac_test_hmac256_vectors 9.440s 323.119us 1 1 100.00
hmac_test_hmac384_vectors 8.060s 489.121us 1 1 100.00
hmac_test_hmac512_vectors 10.840s 330.712us 1 1 100.00
hmac_stress_all 298.400s 320790.379us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 298.400s 320790.379us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.630s 67.681us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 35.054us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.330s 187.471us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.330s 187.471us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.820s 66.468us 1 1 100.00
hmac_csr_rw 0.730s 22.711us 1 1 100.00
hmac_csr_aliasing 2.600s 196.636us 1 1 100.00
hmac_same_csr_outstanding 2.280s 809.162us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.820s 66.468us 1 1 100.00
hmac_csr_rw 0.730s 22.711us 1 1 100.00
hmac_csr_aliasing 2.600s 196.636us 1 1 100.00
hmac_same_csr_outstanding 2.280s 809.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.940s 92.959us 1 1 100.00
hmac_tl_intg_err 3.210s 234.265us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.210s 234.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.570s 333.930us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.780s 827.042us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 95.340s 33430.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.600s 292.399us 1 1 100.00