Simulation Results

Simulation Results: i2c

11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.22 %

code
81.61 %

assert
96.19 %

func
80.87 %

line
96.41 %

branch
92.33 %

cond
85.01 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	41.710s	2718.849us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.430s	5061.743us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.040s	44.245us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.950s	29.867us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.340s	184.657us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.720s	423.034us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.990s	50.063us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.950s	29.867us	1	1	100.00
	i2c_csr_aliasing	1.720s	423.034us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.060s	275.545us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	120.370s	8478.658us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	14.920s	7837.194us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.790s	50.917us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	63.170s	3535.307us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	33.060s	8983.011us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.980s	435.615us	1	1	100.00
	i2c_host_fifo_fmt_empty	17.800s	1674.048us	1	1	100.00
	i2c_host_fifo_reset_rx	3.600s	675.772us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	33.680s	2095.602us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.140s	697.623us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.690s	117.715us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.090s	1962.736us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	53.160s	38293.570us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.970s	10931.726us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	20.230s	3946.570us	1	1	100.00
	i2c_target_intr_smoke	4.610s	8621.460us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.180s	428.436us	1	1	100.00
	i2c_target_fifo_reset_tx	1.530s	536.123us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	54.660s	41728.441us	1	1	100.00
	i2c_target_stress_rd	20.230s	3946.570us	1	1	100.00
	i2c_target_intr_stress_wr	2.930s	3315.733us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.460s	20565.593us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	3.950s	10050.649us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.300s	1201.046us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.200s	341.290us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.700s	363.257us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.070s	341.750us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	14.920s	7837.194us	1	1	100.00
	i2c_host_perf_precise	22.120s	2574.757us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.140s	697.623us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	8.590s	987.022us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.060s	3142.514us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.020s	3929.077us	1	1	100.00
	i2c_target_nack_txstretch	1.100s	649.206us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.180s	313.309us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.430s	761.179us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.940s	17.170us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.840s	21.077us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.900s	42.609us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.900s	42.609us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.040s	44.245us	1	1	100.00
	i2c_csr_rw	0.950s	29.867us	1	1	100.00
	i2c_csr_aliasing	1.720s	423.034us	1	1	100.00
	i2c_same_csr_outstanding	1.030s	20.122us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.040s	44.245us	1	1	100.00
	i2c_csr_rw	0.950s	29.867us	1	1	100.00
	i2c_csr_aliasing	1.720s	423.034us	1	1	100.00
	i2c_same_csr_outstanding	1.030s	20.122us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.380s	268.632us	1	1	100.00
	i2c_sec_cm	0.890s	72.199us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.380s	268.632us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.970s	1041.161us	1
target_error_intr				1
	i2c_target_unexp_stop	1.140s	158.170us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.050s	1410.908us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	50825314592281111984200204637845476711660358490761725989658193599518733307020	152	UVM_INFO @ 275545160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	25606922328740505545065978630871685229498629179434165908712588327901776732729	128	UVM_INFO @ 8478657908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	93664602525113752666021530097736393276177076197219581659627279369264379930857	91	UVM_INFO @ 1410908216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	73492396046258641851147935127996732207223002372815309353284634764499579850961	84	UVM_INFO @ 1962735817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	15578685228175421800421606128547644100005443713806303968976307099119828422463	78	UVM_INFO @ 10050648526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	89423790763759286830867364847004682178140711643998121861460449615048415319511	78	UVM_INFO @ 158169540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	35288093258786550734543850587492494841488074138512839135326825632582184452446	87	UVM_INFO @ 1041161030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---