Simulation Results: lc_ctrl/volatile_unlock_disabled

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.40 %
  • code
  • 84.02 %
  • assert
  • 94.13 %
  • func
  • 93.06 %
  • line
  • 97.15 %
  • branch
  • 93.56 %
  • cond
  • 79.31 %
  • toggle
  • 86.52 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.010s 1221.596us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.290s 74.640us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.180s 236.146us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.260s 28.389us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 73.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.330s 19.322us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.180s 236.146us 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 73.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.480s 145.819us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.030s 213.550us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.210s 23.163us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.200s 1626.657us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 2.110s 80.565us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_prog_failure 2.200s 1626.657us 1 1 100.00
lc_ctrl_errors 2.110s 80.565us 0 1 0.00
lc_ctrl_security_escalation 7.570s 729.759us 1 1 100.00
lc_ctrl_jtag_state_failure 45.860s 3149.036us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.320s 185.120us 1 1 100.00
lc_ctrl_jtag_errors 24.120s 12028.881us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.290s 289.341us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.560s 1079.624us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.320s 185.120us 1 1 100.00
lc_ctrl_jtag_errors 24.120s 12028.881us 1 1 100.00
lc_ctrl_jtag_access 4.550s 5736.903us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.890s 4326.445us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.860s 106.748us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.110s 177.503us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 22.370s 2811.103us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.630s 640.982us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.370s 18.017us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.960s 285.361us 1 1 100.00
lc_ctrl_jtag_alert_test 1.480s 106.642us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.310s 3644.517us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 27.453us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 348.660s 61474.336us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.420s 362.790us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.520s 49.457us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.520s 49.457us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.290s 74.640us 1 1 100.00
lc_ctrl_csr_rw 1.180s 236.146us 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 73.832us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 181.362us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.290s 74.640us 1 1 100.00
lc_ctrl_csr_rw 1.180s 236.146us 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 73.832us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 181.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
lc_ctrl_tl_intg_err 1.450s 59.641us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.450s 59.641us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.030s 213.550us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.390s 174.937us 1 1 100.00
lc_ctrl_sec_cm 5.860s 909.913us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.570s 729.759us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.480s 145.819us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.560s 1079.624us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.640s 834.298us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.640s 834.298us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.890s 1483.276us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.640s 1964.816us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.640s 1964.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 28.670s 6305.075us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 33045939856828421534021009595996332218008487645003282737680455806938948466997 491
UVM_INFO @ 80565437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 100852470755386801438714734725182580383642689392744457712056319714958608416032 5809
UVM_INFO @ 6305075428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---