Simulation Results: lc_ctrl/volatile_unlock_enabled

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.49 %
  • code
  • 83.74 %
  • assert
  • 94.13 %
  • func
  • 93.59 %
  • line
  • 97.08 %
  • branch
  • 93.37 %
  • cond
  • 78.94 %
  • toggle
  • 85.75 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.310s 119.437us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.070s 16.322us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.780s 181.724us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.370s 145.831us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 103.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.880s 23.175us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.780s 181.724us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 103.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.550s 130.700us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 15.970s 1455.296us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.730s 23.231us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.340s 57.460us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.750s 634.344us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_prog_failure 1.340s 57.460us 1 1 100.00
lc_ctrl_errors 4.750s 634.344us 1 1 100.00
lc_ctrl_security_escalation 4.360s 310.964us 1 1 100.00
lc_ctrl_jtag_state_failure 27.770s 2193.519us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.750s 820.194us 1 1 100.00
lc_ctrl_jtag_errors 24.710s 1765.948us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.520s 209.477us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.270s 1918.803us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.750s 820.194us 1 1 100.00
lc_ctrl_jtag_errors 24.710s 1765.948us 1 1 100.00
lc_ctrl_jtag_access 4.570s 473.440us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.230s 1866.927us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.590s 116.511us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.180s 72.805us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.480s 10565.217us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.950s 564.136us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.110s 147.568us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.450s 560.191us 1 1 100.00
lc_ctrl_jtag_alert_test 0.940s 37.389us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.330s 1083.658us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 38.041us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 169.360s 63894.862us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.120s 95.458us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.290s 671.009us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.290s 671.009us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.070s 16.322us 1 1 100.00
lc_ctrl_csr_rw 0.780s 181.724us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 103.775us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 23.179us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.070s 16.322us 1 1 100.00
lc_ctrl_csr_rw 0.780s 181.724us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 103.775us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 23.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
lc_ctrl_tl_intg_err 1.460s 268.729us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.460s 268.729us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 15.970s 1455.296us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.350s 716.479us 1 1 100.00
lc_ctrl_sec_cm 5.360s 2356.446us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.360s 310.964us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.550s 130.700us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.270s 1918.803us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.270s 7258.241us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.270s 7258.241us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.800s 2964.469us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.800s 243.104us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.800s 243.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 42.380s 9191.955us 1 1 100.00