Simulation Results: pattgen

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 36.871us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 47.689us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 45.827us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 199.994us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 33.209us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 17.281us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 45.827us 1 1 100.00
pattgen_csr_aliasing 1.000s 33.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 498.000s 44630.139us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 11.000s 5172.555us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 47.960us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 30.000s 4060.580us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 45.583us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 42.560us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 87.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 87.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 47.689us 1 1 100.00
pattgen_csr_rw 1.000s 45.827us 1 1 100.00
pattgen_csr_aliasing 1.000s 33.209us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 24.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 47.689us 1 1 100.00
pattgen_csr_rw 1.000s 45.827us 1 1 100.00
pattgen_csr_aliasing 1.000s 33.209us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 24.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 52.663us 1 1 100.00
pattgen_sec_cm 1.000s 65.360us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 52.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 41.000s 21668.146us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 19.000s 10026.706us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
pattgen_inactive_level 35368895694757713665132220808010303926948779935859587176550959802058089623907 99
UVM_INFO @ 10026705952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 29956142018214708327436540008221916617075330003166319034189046352227142766636 179
UVM_ERROR @ 7628512458 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7628512458 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 7628781692 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]