Simulation Results

Simulation Results: pwrmgr

11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
93.79 %

code
90.08 %

assert
96.08 %

func
95.22 %

line
98.92 %

branch
95.42 %

cond
94.06 %

toggle
90.02 %

FSM
72.00 %

Validation stages

V1		100.00%
V2		86.67%
V2S		80.00%
V3		50.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	pwrmgr_smoke	0.690s	30.718us	1	1	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.760s	69.426us	1	1	100.00
csr_rw				1	1	100.00
	pwrmgr_csr_rw	0.770s	40.089us	1	1	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	1.580s	486.687us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	0.900s	33.613us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	0.950s	39.807us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	pwrmgr_csr_rw	0.770s	40.089us	1	1	100.00
	pwrmgr_csr_aliasing	0.900s	33.613us	1	1	100.00

13/15 passed

86.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				1	1	100.00
	pwrmgr_wakeup	0.580s	96.173us	1	1	100.00
control_clks				1	1	100.00
	pwrmgr_wakeup	0.580s	96.173us	1	1	100.00
aborted_low_power				2	2	100.00
	pwrmgr_aborted_low_power	1.090s	81.229us	1	1	100.00
	pwrmgr_lowpower_invalid	0.730s	47.320us	1	1	100.00
reset				1	2	50.00
	pwrmgr_reset	0.920s	49.542us	1	1	100.00
	pwrmgr_reset_invalid	0.650s	71.770us	0	1	0.00
main_power_glitch_reset				1	1	100.00
	pwrmgr_reset	0.920s	49.542us	1	1	100.00
reset_wakeup_race				1	1	100.00
	pwrmgr_wakeup_reset	0.970s	235.492us	1	1	100.00
lowpower_wakeup_race				1	1	100.00
	pwrmgr_lowpower_wakeup_race	0.820s	93.527us	1	1	100.00
disable_rom_integrity_check				0	1	0.00
	pwrmgr_disable_rom_integrity_check	1.410s	1000.000us	0	1	0.00
stress_all				1	1	100.00
	pwrmgr_stress_all	1.170s	470.588us	1	1	100.00
intr_test				1	1	100.00
	pwrmgr_intr_test	0.640s	22.200us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	pwrmgr_tl_errors	1.420s	388.306us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	pwrmgr_tl_errors	1.420s	388.306us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.760s	69.426us	1	1	100.00
	pwrmgr_csr_rw	0.770s	40.089us	1	1	100.00
	pwrmgr_csr_aliasing	0.900s	33.613us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.670s	280.014us	1	1	100.00
tl_d_partial_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.760s	69.426us	1	1	100.00
	pwrmgr_csr_rw	0.770s	40.089us	1	1	100.00
	pwrmgr_csr_aliasing	0.900s	33.613us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.670s	280.014us	1	1	100.00

V2S

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	pwrmgr_tl_intg_err	0.650s	11.238us	0	1	0.00
	pwrmgr_sec_cm	0.730s	20.346us	0	1	0.00
prim_count_check				0	1	0.00
	pwrmgr_sec_cm	0.730s	20.346us	0	1	0.00
prim_fsm_check				0	1	0.00
	pwrmgr_sec_cm	0.730s	20.346us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	pwrmgr_tl_intg_err	0.650s	11.238us	0	1	0.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.610s	1277.454us	1	1	100.00
sec_cm_rom_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_wakeup_reset	0.970s	235.492us	1	1	100.00
sec_cm_rstmgr_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.940s	158.273us	1	1	100.00
sec_cm_esc_rx_clk_bkgn_chk				1	1	100.00
	pwrmgr_esc_clk_rst_malfunc	0.600s	41.215us	1	1	100.00
sec_cm_esc_rx_clk_local_esc				0	1	0.00
	pwrmgr_sec_cm	0.730s	20.346us	0	1	0.00
sec_cm_fsm_sparse				0	1	0.00
	pwrmgr_sec_cm	0.730s	20.346us	0	1	0.00
sec_cm_fsm_terminal				0	1	0.00
	pwrmgr_sec_cm	0.730s	20.346us	0	1	0.00
sec_cm_ctrl_flow_global_esc				1	1	100.00
	pwrmgr_global_esc	0.620s	83.106us	1	1	100.00
sec_cm_main_pd_rst_local_esc				1	1	100.00
	pwrmgr_glitch	0.640s	33.719us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	1.030s	174.314us	1	1	100.00
sec_cm_wakeup_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.770s	40.089us	1	1	100.00
sec_cm_reset_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.770s	40.089us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				0	1	0.00
	pwrmgr_escalation_timeout	0.790s	233.873us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	pwrmgr_stress_all_with_rand_reset	1.890s	810.888us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire				2 test runs
	pwrmgr_tl_intg_err	87106815951229375705406522336194103601856451955311805463996190657561057688187	82	UVM_INFO @ 11238258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_sec_cm	101520207432890822595552176189686189362751070003750307517797699357324989368541	81	UVM_INFO @ 20345585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!clk_en) \|\| status)'				1 test run
	pwrmgr_escalation_timeout	115710182774636292023674811550684314295040449057636481198740831525602859484421	79	UVM_ERROR @ 233873319 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A UVM_INFO @ 233873319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	pwrmgr_disable_rom_integrity_check	95774538653344784502700991990682974399365151293218918383605320627691146829734	83	UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks				1 test run
	pwrmgr_reset_invalid	101721481097559059179394377794409462260129521718390934674483527416409149951038	86	UVM_INFO @ 71770487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---