Simulation Results: rom_ctrl/32kb

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.22 %
  • code
  • 97.84 %
  • assert
  • 96.80 %
  • func
  • 94.03 %
  • line
  • 99.32 %
  • branch
  • 98.54 %
  • cond
  • 98.07 %
  • toggle
  • 99.92 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.780s 224.771us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.430s 554.462us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.550s 538.172us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.430s 127.105us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 297.348us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.160s 548.837us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.550s 538.172us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 297.348us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.440s 126.198us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.440s 867.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.780s 413.002us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.470s 1612.039us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.840s 713.986us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.570s 123.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.300s 164.121us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.300s 164.121us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.430s 554.462us 1 1 100.00
rom_ctrl_csr_rw 3.550s 538.172us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 297.348us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.600s 124.367us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.430s 554.462us 1 1 100.00
rom_ctrl_csr_rw 3.550s 538.172us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 297.348us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.600s 124.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.860s 605.548us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 204.740s 1138.737us 1 1 100.00
rom_ctrl_tl_intg_err 24.230s 320.368us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 204.740s 1138.737us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 204.740s 1138.737us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 204.740s 1138.737us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 204.740s 1138.737us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.780s 224.771us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.780s 224.771us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.780s 224.771us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.230s 320.368us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
rom_ctrl_kmac_err_chk 5.840s 713.986us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 79.580s 3372.301us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.860s 605.548us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 204.740s 1138.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 40.660s 1634.494us 1 1 100.00