Simulation Results: rv_timer

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.830s 1318.314us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.660s 26.996us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 26.355us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.080s 1523.566us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 60.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.660s 13.906us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 26.355us 1 1 100.00
rv_timer_csr_aliasing 0.730s 60.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.690s 212.120us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.580s 1162.593us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 139.720s 417309.178us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 139.720s 417309.178us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.260s 4296.672us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 43.558us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 44.688us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.480s 104.244us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.480s 104.244us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 26.996us 1 1 100.00
rv_timer_csr_rw 0.560s 26.355us 1 1 100.00
rv_timer_csr_aliasing 0.730s 60.140us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 55.355us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 26.996us 1 1 100.00
rv_timer_csr_rw 0.560s 26.355us 1 1 100.00
rv_timer_csr_aliasing 0.730s 60.140us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 55.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.740s 67.692us 1 1 100.00
rv_timer_tl_intg_err 0.830s 144.655us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.830s 144.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.730s 219.239us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.840s 43.141us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 16.120s 2680.495us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 65695896548452663413805281855614584930348104986460912187004291846304716391224 75
UVM_INFO @ 219238882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 109608902764876173969820040784705667284207902117783146713589578093327391828063 75
UVM_INFO @ 212119601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 108601801905898826232532438053682422733555810915477633037379877569008809992804 76
UVM_INFO @ 43140529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---