Simulation Results: spi_device/2p

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.68 %
  • code
  • 94.04 %
  • assert
  • 94.62 %
  • func
  • 71.38 %
  • line
  • 98.92 %
  • branch
  • 98.25 %
  • cond
  • 95.95 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 129.910s 45179.963us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.300s 158.263us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.140s 117.907us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 27.250s 10865.351us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.150s 634.076us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.570s 211.421us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.140s 117.907us 1 1 100.00
spi_device_csr_aliasing 15.150s 634.076us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.710s 52.045us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.350s 31.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 38.099us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.950s 31.027us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.780s 27.036us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.160s 200.117us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.160s 200.117us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 11.420s 4326.776us 1 1 100.00
spi_device_tpm_sts_read 0.890s 96.696us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 28.120s 13575.446us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.920s 982.232us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.020s 2661.959us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.020s 2661.959us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.340s 3236.496us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.340s 3236.496us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.340s 3236.496us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.340s 3236.496us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.340s 3236.496us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.870s 1031.786us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 30.330s 4794.955us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 30.330s 4794.955us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 30.330s 4794.955us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.140s 507.812us 1 1 100.00
spi_device_read_buffer_direct 6.850s 805.368us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 30.330s 4794.955us 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 59.960s 9440.728us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 9.000s 7826.098us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 9.000s 7826.098us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 129.910s 45179.963us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 114.050s 14433.889us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 130.740s 77834.775us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.710s 12.149us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.930s 52.221us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.560s 152.003us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.560s 152.003us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.300s 158.263us 1 1 100.00
spi_device_csr_rw 1.140s 117.907us 1 1 100.00
spi_device_csr_aliasing 15.150s 634.076us 1 1 100.00
spi_device_same_csr_outstanding 3.160s 222.580us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.300s 158.263us 1 1 100.00
spi_device_csr_rw 1.140s 117.907us 1 1 100.00
spi_device_csr_aliasing 15.150s 634.076us 1 1 100.00
spi_device_same_csr_outstanding 3.160s 222.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.060s 368.765us 1 1 100.00
spi_device_tl_intg_err 6.790s 383.621us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.790s 383.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 85.990s 84367.093us 1 1 100.00