Simulation Results: sram_ctrl/main

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 96.72 %
  • assert
  • 96.19 %
  • func
  • 94.00 %
  • block
  • 96.01 %
  • line
  • 96.81 %
  • branch
  • 94.17 %
  • toggle
  • 95.89 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 465.116us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.715us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.137us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 125.689us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 725.664us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 37.137us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.793us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 116.000s 35916.816us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 99.000s 9813.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 29.000s 7012.929us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 161.000s 4165.501us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 147.000s 58726.657us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 31.000s 34969.372us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 25.000s 33637.667us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 11896.711us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 753.347us 1 1 100.00
sram_ctrl_partial_access_b2b 290.000s 265826.192us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 718.758us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 5538.682us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 695.526us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 5162.534us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 343.701us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 79.000s 66300.082us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 29.918us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 385.442us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 385.442us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.715us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.137us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.793us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.074us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.715us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.137us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.793us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 14670.918us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 2984.447us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 357.247us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 2984.447us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 357.247us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 5162.534us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 5162.534us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.137us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 11896.711us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 11896.711us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 11896.711us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 25.000s 33637.667us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 2388.019us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 14670.918us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 9472.598us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 465.116us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 465.116us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 11896.711us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 2984.447us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 25.000s 33637.667us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 2984.447us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2984.447us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 465.116us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2984.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.000s 8448.787us 1 1 100.00