Simulation Results: sram_ctrl/ret

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.40 %
  • code
  • 83.36 %
  • assert
  • 96.43 %
  • func
  • 94.40 %
  • block
  • 93.80 %
  • line
  • 94.97 %
  • branch
  • 89.51 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 45.265us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 107.038us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.242us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 87.727us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.967us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 42.352us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 35.242us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.967us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 174.100us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 193.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 2606.787us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 135.000s 11607.730us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 314.241us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 1719.755us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 4057.378us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 326.578us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 75.433us 1 1 100.00
sram_ctrl_partial_access_b2b 151.000s 37637.333us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 80.819us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 72.714us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 72.295us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 153.434us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 38.412us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 20.000s 10575.931us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 11.763us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 112.737us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 112.737us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 107.038us 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.242us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.967us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 118.862us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 107.038us 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.242us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.967us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 118.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 239.555us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 725.892us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 267.898us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 725.892us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 267.898us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 153.434us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 153.434us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 35.242us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 326.578us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 326.578us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 326.578us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 4057.378us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 321.719us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 239.555us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 36.432us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 45.265us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 45.265us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 326.578us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 725.892us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 4057.378us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 725.892us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 725.892us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 45.265us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 725.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 24.000s 1448.294us 1 1 100.00