Simulation Results: sysrst_ctrl

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.37 %
  • code
  • 89.30 %
  • assert
  • 87.93 %
  • func
  • 66.87 %
  • line
  • 95.16 %
  • branch
  • 96.03 %
  • cond
  • 93.11 %
  • toggle
  • 100.00 %
  • FSM
  • 62.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.270s 2135.273us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.390s 2453.276us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.660s 2191.280us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.610s 2350.837us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.320s 6042.184us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.900s 2052.988us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 18.100s 38943.372us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.130s 2291.139us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.230s 2041.471us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.900s 2052.988us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.130s 2291.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 196.650s 107742.165us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 181.260s 111737.594us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.740s 3036.319us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.930s 3049.791us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.360s 2584.864us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.100s 2024.533us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.810s 3031.381us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.240s 2621.613us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 112.510s 1344841.633us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 17.030s 33427.570us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 569.080s 310837.738us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.480s 2025.748us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.370s 2009.118us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.070s 2044.098us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.070s 2044.098us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.320s 6042.184us 1 1 100.00
sysrst_ctrl_csr_rw 4.900s 2052.988us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.130s 2291.139us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.380s 4876.965us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.320s 6042.184us 1 1 100.00
sysrst_ctrl_csr_rw 4.900s 2052.988us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.130s 2291.139us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.380s 4876.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 37.180s 22015.628us 1 1 100.00
sysrst_ctrl_tl_intg_err 22.410s 42531.892us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 22.410s 42531.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.990s 2586.215us 1 1 100.00