Simulation Results: uart

 
11/05/2026 15:30:27 DVSim: v1.34.0 sha: 62066fe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.49 %
  • code
  • 96.74 %
  • assert
  • 97.12 %
  • func
  • 62.60 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.500s 709.515us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.630s 38.233us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.650s 15.035us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.360s 224.853us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.100s 56.234us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.090s 39.074us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.650s 15.035us 1 1 100.00
uart_csr_aliasing 1.100s 56.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 52.030s 145164.068us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.500s 709.515us 1 1 100.00
uart_tx_rx 52.030s 145164.068us 1 1 100.00
parity_error 2 2 100.00
uart_intr 15.470s 51283.944us 1 1 100.00
uart_rx_parity_err 75.640s 105439.914us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 52.030s 145164.068us 1 1 100.00
uart_intr 15.470s 51283.944us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 137.610s 119205.017us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 134.120s 131483.363us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 13.580s 41317.475us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 15.470s 51283.944us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 15.470s 51283.944us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 15.470s 51283.944us 1 1 100.00
perf 1 1 100.00
uart_perf 67.270s 16197.644us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 15.910s 9386.141us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 15.910s 9386.141us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 54.830s 45687.216us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.750s 5282.227us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 11.570s 11976.827us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.090s 2968.141us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 241.930s 129801.186us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 461.660s 356659.430us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.790s 17.386us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 14.917us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.240s 33.358us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.240s 33.358us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.630s 38.233us 1 1 100.00
uart_csr_rw 0.650s 15.035us 1 1 100.00
uart_csr_aliasing 1.100s 56.234us 1 1 100.00
uart_same_csr_outstanding 0.740s 56.864us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.630s 38.233us 1 1 100.00
uart_csr_rw 0.650s 15.035us 1 1 100.00
uart_csr_aliasing 1.100s 56.234us 1 1 100.00
uart_same_csr_outstanding 0.740s 56.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.750s 158.098us 1 1 100.00
uart_tl_intg_err 1.150s 92.755us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.150s 92.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 8.070s 14379.079us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 20637309540889235819277175317795987094862227739313839208223562681217433856079 76
UVM_ERROR @ 2014535559 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2014555559 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2014565559 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2014665559 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 215 [0xd7]) reg name: uart_reg_block.rdata