Simulation Results: adc_ctrl

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.84 %
  • code
  • 93.29 %
  • assert
  • 91.09 %
  • func
  • 13.14 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 86.02 %
  • toggle
  • 99.76 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 3.440s 5929.991us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.950s 749.180us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.540s 434.623us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 69.850s 26388.005us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.650s 838.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.770s 569.299us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.540s 434.623us 1 1 100.00
adc_ctrl_csr_aliasing 1.650s 838.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.410s 495.407us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.800s 444.795us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.850s 416.134us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.060s 417.857us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.770s 289.934us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.780s 417.129us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.140s 417.822us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.500s 498.474us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.470s 3728.499us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 13.450s 34134.211us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 26.070s 133816.673us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.390s 794.890us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.670s 460.807us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.100s 280.556us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.540s 1078.142us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.540s 1078.142us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.950s 749.180us 1 1 100.00
adc_ctrl_csr_rw 1.540s 434.623us 1 1 100.00
adc_ctrl_csr_aliasing 1.650s 838.533us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.350s 2693.620us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.950s 749.180us 1 1 100.00
adc_ctrl_csr_rw 1.540s 434.623us 1 1 100.00
adc_ctrl_csr_aliasing 1.650s 838.533us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.350s 2693.620us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.370s 7737.065us 1 1 100.00
adc_ctrl_tl_intg_err 3.180s 4810.532us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.180s 4810.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.030s 789.391us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 47019658982277589289340227640669656795526875286163751604560877075296011236316 394
UVM_INFO @ 495407384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 61770593169779743695400847031833142927361370287525754066709281280863101896700 394
UVM_INFO @ 444795172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 14652596995058616443756358991340648163350740665969307291006727870533715878503 394
UVM_INFO @ 416133524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 31903832800839217185369482471514329198423998002144966333169421110145780575329 394
UVM_INFO @ 417857310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 83146956816913499648855739811806205838745986595396180468362874152404886511540 394
UVM_INFO @ 289934315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 109810234669268591978925500241244484441282225380114315594410677031313554528641 394
UVM_INFO @ 417129109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 73648393870013402683939493238024187462401704314175395070437142630774216923636 394
UVM_INFO @ 498474039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 51670761629416973332974970024609389050767718191945151569985290670689026871726 394
UVM_INFO @ 417822311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 115604013037539299142591237673583665962839580449198550394674967487969921312848 414
UVM_INFO @ 789391356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 112989716887661437713296308069593661198172316005962754956275190731207998548067 395
UVM_INFO @ 794889704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---