Simulation Results: alert_handler

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.80 %
  • code
  • 89.42 %
  • assert
  • 90.79 %
  • func
  • 77.20 %
  • line
  • 99.62 %
  • branch
  • 98.42 %
  • cond
  • 91.30 %
  • toggle
  • 86.79 %
  • FSM
  • 70.97 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 16.870s 764.704us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.670s 37.334us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.340s 181.935us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 74.340s 1948.655us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 47.320s 539.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 8.120s 147.621us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.340s 181.935us 1 1 100.00
alert_handler_csr_aliasing 47.320s 539.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 138.590s 7578.967us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 12.440s 295.507us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 783.590s 117929.235us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 13.380s 372.782us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 16.870s 764.704us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 6.110s 231.996us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 22.570s 626.896us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 31.890s 1987.189us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1159.900s 67361.027us 1 1 100.00
alert_handler_lpg_stub_clk 938.800s 33781.053us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 747.200s 127298.282us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.560s 354.614us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.020s 110.415us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.130s 7.541us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.450s 111.854us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.450s 111.854us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.670s 37.334us 1 1 100.00
alert_handler_csr_rw 3.340s 181.935us 1 1 100.00
alert_handler_csr_aliasing 47.320s 539.474us 1 1 100.00
alert_handler_same_csr_outstanding 28.120s 7227.971us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.670s 37.334us 1 1 100.00
alert_handler_csr_rw 3.340s 181.935us 1 1 100.00
alert_handler_csr_aliasing 47.320s 539.474us 1 1 100.00
alert_handler_same_csr_outstanding 28.120s 7227.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 123.840s 3212.593us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 123.840s 3212.593us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 123.840s 3212.593us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 123.840s 3212.593us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 213.380s 4370.071us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
alert_handler_tl_intg_err 2.510s 58.773us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.510s 58.773us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 123.840s 3212.593us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 16.870s 764.704us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 16.870s 764.704us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 16.870s 764.704us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 16.870s 764.704us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.380s 372.782us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1159.900s 67361.027us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.380s 372.782us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 783.590s 117929.235us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 783.590s 117929.235us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.650s 3420.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 41.400s 1245.861us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 82440675284290380027129514732927320529309539820382323889894497470164532114462 207
UVM_INFO @ 354614106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 45571718331182856901014695833445321654581149899509177386355178130741312512677 113
UVM_INFO @ 1245860943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---