Simulation Results: chip

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.68 %
  • code
  • 84.81 %
  • assert
  • 97.37 %
  • func
  • 50.85 %
  • line
  • 94.30 %
  • branch
  • 93.09 %
  • cond
  • 88.33 %
  • toggle
  • 91.19 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.70%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 110.150s 2690.888us 1 1 100.00
chip_sw_example_rom 57.590s 2525.689us 1 1 100.00
chip_sw_example_manufacturer 114.900s 2830.289us 1 1 100.00
chip_sw_example_concurrency 115.040s 2656.359us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 147.220s 4436.689us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 486.180s 6541.067us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2103.650s 31079.822us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3560.090s 29176.375us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 56.580s 1968.797us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3560.090s 29176.375us 1 1 100.00
chip_csr_rw 486.180s 6541.067us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.790s 154.108us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 283.840s 4085.330us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 283.840s 4085.330us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 283.840s 4085.330us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 325.520s 4914.149us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 325.520s 4914.149us 1 1 100.00
chip_sw_uart_tx_rx_idx1 328.920s 4920.732us 1 1 100.00
chip_sw_uart_tx_rx_idx2 333.250s 4420.795us 1 1 100.00
chip_sw_uart_tx_rx_idx3 290.790s 4636.180us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1512.390s 13359.115us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 929.450s 8738.757us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 222.750s 4101.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 129.970s 4215.497us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 129.970s 4215.497us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 164.040s 2957.441us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 140.390s 3763.170us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 156.230s 4622.299us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 82.770s 2695.361us 1 1 100.00
chip_tap_straps_testunlock0 166.370s 4210.908us 1 1 100.00
chip_tap_straps_rma 103.440s 3352.191us 1 1 100.00
chip_tap_straps_prod 76.340s 2802.775us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 156.850s 2940.307us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 626.240s 9261.032us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 386.970s 6572.299us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 386.970s 6572.299us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 537.390s 7764.705us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1398.760s 13873.367us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.890s 4433.356us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 510.240s 5950.919us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3374.830s 18767.375us 1 1 100.00
chip_sw_aes_enc_jitter_en 136.990s 2682.962us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 540.640s 6058.114us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.030s 2892.549us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1356.250s 13562.237us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 160.720s 3398.101us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 272.680s 5134.414us 1 1 100.00
chip_sw_clkmgr_jitter 96.420s 2375.180us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 147.420s 3004.112us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 524.990s 8127.884us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 221.710s 5428.568us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 133.030s 3015.175us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 221.710s 5428.568us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 127.270s 3177.044us 1 1 100.00
chip_sw_aes_smoketest 164.550s 3101.565us 1 1 100.00
chip_sw_aon_timer_smoketest 138.250s 3608.393us 1 1 100.00
chip_sw_clkmgr_smoketest 140.120s 3111.773us 1 1 100.00
chip_sw_csrng_smoketest 142.430s 3305.100us 1 1 100.00
chip_sw_entropy_src_smoketest 854.620s 7609.531us 1 1 100.00
chip_sw_gpio_smoketest 137.710s 3410.182us 1 1 100.00
chip_sw_hmac_smoketest 177.860s 3641.654us 1 1 100.00
chip_sw_kmac_smoketest 142.260s 2962.030us 1 1 100.00
chip_sw_otbn_smoketest 1353.900s 11403.614us 1 1 100.00
chip_sw_pwrmgr_smoketest 197.500s 6162.860us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 217.560s 6117.099us 1 1 100.00
chip_sw_rv_plic_smoketest 96.480s 2801.404us 1 1 100.00
chip_sw_rv_timer_smoketest 149.730s 3099.133us 1 1 100.00
chip_sw_rstmgr_smoketest 141.840s 2399.625us 1 1 100.00
chip_sw_sram_ctrl_smoketest 110.240s 2469.009us 1 1 100.00
chip_sw_uart_smoketest 152.310s 3077.405us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 153.230s 2778.481us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 271.660s 4917.907us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7927.730s 64072.954us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2940.630s 15240.444us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 66.996s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 186.000s 3632.206us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 139.330s 3343.664us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6500.370s 54522.812us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7534.980s 58330.912us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 56.690s 2531.108us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 56.690s 2531.108us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3560.090s 29176.375us 1 1 100.00
chip_same_csr_outstanding 1544.990s 14678.544us 1 1 100.00
chip_csr_hw_reset 147.220s 4436.689us 1 1 100.00
chip_csr_rw 486.180s 6541.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3560.090s 29176.375us 1 1 100.00
chip_same_csr_outstanding 1544.990s 14678.544us 1 1 100.00
chip_csr_hw_reset 147.220s 4436.689us 1 1 100.00
chip_csr_rw 486.180s 6541.067us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 27.290s 576.871us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.050s 44.378us 1 1 100.00
xbar_smoke_large_delays 48.690s 8891.649us 1 1 100.00
xbar_smoke_slow_rsp 42.320s 5335.278us 1 1 100.00
xbar_random_zero_delays 10.020s 162.873us 1 1 100.00
xbar_random_large_delays 215.090s 41360.911us 1 1 100.00
xbar_random_slow_rsp 85.800s 10714.410us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 16.430s 692.952us 1 1 100.00
xbar_error_and_unmapped_addr 5.030s 43.883us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 46.990s 2316.251us 1 1 100.00
xbar_error_and_unmapped_addr 5.030s 43.883us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 40.410s 1808.661us 1 1 100.00
xbar_access_same_device_slow_rsp 680.410s 89261.881us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 9.700s 476.252us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 122.880s 3008.970us 1 1 100.00
xbar_stress_all_with_error 139.260s 8185.482us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 232.570s 5168.808us 1 1 100.00
xbar_stress_all_with_reset_error 48.360s 210.561us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2940.630s 15240.444us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2197.650s 28405.453us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2820.110s 16698.962us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 12.599s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 22.516s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 17.137s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 11.099s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 20.060s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 87.067s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 7.295s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 7.266s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 53.945s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 46.881s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 167.178s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 44.731s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 64.398s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 42.849s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 27.525s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.460s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.340s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.110s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16.910s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.370s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.920s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.750s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.570s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.620s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.390s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 15.810s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.620s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 15.860s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 15.830s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 15.670s 10.100us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 115.147s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 40.014s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 29.715s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 63.636s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 25.220s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5571.190s 28530.209us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5584.500s 29117.452us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5567.110s 29297.906us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2829.310s 15968.679us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2524.630s 34595.928us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2524.630s 34595.928us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 141.280s 3014.740us 1 1 100.00
chip_sw_aes_enc_jitter_en 136.990s 2682.962us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 186.110s 3086.645us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 130.030s 3298.606us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 681.190s 7116.932us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 142.430s 3276.041us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 285.060s 5091.011us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 476.120s 5541.199us 1 1 100.00
chip_plic_all_irqs_10 260.710s 3945.077us 1 1 100.00
chip_plic_all_irqs_20 337.060s 4322.578us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 168.990s 3297.581us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1005.910s 11496.785us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 167.750s 2829.989us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 110.620s 2503.768us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.148s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 590.990s 6550.053us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 636.600s 6558.332us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 685.220s 8364.601us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8524.580s 254860.577us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 189.950s 3536.833us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 197.500s 6162.860us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 189.950s 3536.833us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 370.290s 8433.146us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 370.290s 8433.146us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 192.090s 6754.647us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 275.090s 4632.867us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 508.240s 6161.047us 1 1 100.00
chip_sw_aes_idle 130.030s 3298.606us 1 1 100.00
chip_sw_hmac_enc_idle 141.750s 2933.500us 1 1 100.00
chip_sw_kmac_idle 103.770s 2715.841us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 315.530s 5067.905us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 244.420s 4691.772us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 190.930s 3533.898us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 219.680s 3694.452us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 574.200s 11116.194us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 301.100s 3679.347us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 323.470s 5449.859us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 335.150s 4317.076us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 323.600s 5014.935us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 370.950s 4447.994us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 322.160s 5345.384us 1 1 100.00
chip_sw_ast_clk_outputs 537.390s 7764.705us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 424.100s 9568.602us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 335.150s 4317.076us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 323.600s 5014.935us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.890s 4433.356us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 510.240s 5950.919us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3374.830s 18767.375us 1 1 100.00
chip_sw_aes_enc_jitter_en 136.990s 2682.962us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 540.640s 6058.114us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.030s 2892.549us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1356.250s 13562.237us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 160.720s 3398.101us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 272.680s 5134.414us 1 1 100.00
chip_sw_clkmgr_jitter 96.420s 2375.180us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 122.360s 2881.432us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 372.850s 5372.366us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 529.980s 7322.855us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3721.680s 25414.692us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 138.810s 3403.309us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 121.210s 2998.716us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 477.290s 7151.424us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 143.640s 3659.018us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 291.380s 5111.572us 1 1 100.00
chip_sw_flash_init_reduced_freq 1204.130s 21311.923us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 11492.810s 132223.865us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 537.390s 7764.705us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 346.790s 4932.794us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 261.700s 3623.676us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 590.990s 6550.053us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1904.250s 24902.662us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 233.390s 4276.580us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 398.210s 6288.249us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 127.500s 2939.956us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2811.480s 18978.806us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 153.430s 2990.525us 1 1 100.00
chip_sw_edn_entropy_reqs 691.420s 6363.156us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 153.430s 2990.525us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1904.250s 24902.662us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 119.010s 2808.516us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1123.510s 21634.827us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 507.380s 5291.565us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 510.240s 5950.919us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 347.650s 4143.858us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.890s 4433.356us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3268.890s 44551.605us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1123.510s 21634.827us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 192.720s 3352.418us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1060.710s 10525.862us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 140.090s 3048.113us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3268.890s 44551.605us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 140.090s 3048.113us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 140.090s 3048.113us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 140.090s 3048.113us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 140.090s 3048.113us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 288.870s 9807.310us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 488.170s 5762.077us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 322.200s 4367.435us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 322.200s 4367.435us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 178.980s 3400.698us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.030s 2892.549us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 141.750s 2933.500us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 825.070s 7611.835us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 571.320s 6068.831us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 355.430s 4856.398us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 362.640s 5299.135us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 300.860s 4482.444us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 289.840s 4115.590us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1060.710s 10525.862us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1356.250s 13562.237us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1449.760s 12487.704us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 681.190s 7116.932us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2434.400s 13348.111us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 126.840s 2388.357us 1 1 100.00
chip_sw_kmac_mode_kmac 152.060s 3451.477us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 160.720s 3398.101us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1060.710s 10525.862us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 140.720s 2889.772us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1082.140s 9614.646us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 103.770s 2715.841us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 285.060s 5091.011us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 82.770s 2695.361us 1 1 100.00
chip_tap_straps_rma 103.440s 3352.191us 1 1 100.00
chip_tap_straps_prod 76.340s 2802.775us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.180s 3224.117us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 843.710s 8252.312us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 140.090s 3048.113us 0 1 0.00
chip_sw_flash_rma_unlocked 3268.890s 44551.605us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 173.650s 3212.515us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 407.430s 6638.300us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 433.320s 6896.439us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 423.340s 6494.369us 0 1 0.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_keymgr_key_derivation 1060.710s 10525.862us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 242.110s 9837.961us 1 1 100.00
chip_sw_sram_ctrl_execution_main 349.790s 6971.028us 1 1 100.00
chip_prim_tl_access 288.870s 9807.310us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 424.100s 9568.602us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 301.100s 3679.347us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 323.470s 5449.859us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 335.150s 4317.076us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 323.600s 5014.935us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 370.950s 4447.994us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 322.160s 5345.384us 1 1 100.00
chip_tap_straps_dev 82.770s 2695.361us 1 1 100.00
chip_tap_straps_rma 103.440s 3352.191us 1 1 100.00
chip_tap_straps_prod 76.340s 2802.775us 1 1 100.00
chip_rv_dm_lc_disabled 143.110s 5042.276us 0 1 0.00
chip_lc_scrap 3 4 75.00
chip_sw_lc_ctrl_rma_to_scrap 123.910s 2874.502us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 73.310s 3726.313us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 72.170s 2971.857us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 1616.670s 26676.617us 0 1 0.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1354.050s 25873.193us 1 1 100.00
chip_rv_dm_lc_disabled 143.110s 5042.276us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 545.770s 10364.311us 0 1 0.00
chip_sw_lc_walkthrough_prod 509.420s 11225.280us 0 1 0.00
chip_sw_lc_walkthrough_prodend 480.840s 7993.314us 1 1 100.00
chip_sw_lc_walkthrough_rma 304.860s 5941.231us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1354.050s 25873.193us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 62.390s 2240.223us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 56.520s 2697.083us 1 1 100.00
rom_volatile_raw_unlock 77.850s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3281.390s 17448.635us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3374.830s 18767.375us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 508.240s 6161.047us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 508.240s 6161.047us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 508.240s 6161.047us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 278.890s 4268.653us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1123.510s 21634.827us 1 1 100.00
chip_sw_otbn_mem_scramble 278.890s 4268.653us 1 1 100.00
chip_sw_keymgr_key_derivation 1060.710s 10525.862us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 359.460s 5444.822us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 144.460s 3533.671us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1123.510s 21634.827us 1 1 100.00
chip_sw_otbn_mem_scramble 278.890s 4268.653us 1 1 100.00
chip_sw_keymgr_key_derivation 1060.710s 10525.862us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 359.460s 5444.822us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 144.460s 3533.671us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 322.230s 5414.706us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 156.180s 3224.117us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 173.650s 3212.515us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 407.430s 6638.300us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 433.320s 6896.439us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 423.340s 6494.369us 0 1 0.00
chip_sw_lc_ctrl_transition 567.550s 12604.530us 1 1 100.00
chip_prim_tl_access 288.870s 9807.310us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 288.870s 9807.310us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 757.180s 8171.084us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 64.290s 2521.271us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1032.640s 28474.794us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 261.900s 7614.251us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 253.330s 6687.040us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 328.800s 7399.185us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 775.500s 24433.267us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 221.630s 5302.899us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 370.290s 8433.146us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 752.990s 13616.427us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 296.210s 5202.343us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 64.290s 2521.271us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 303.300s 5405.851us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 382.020s 8795.504us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 340.140s 7361.255us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 116.690s 3255.914us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1521.880s 23087.054us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 657.530s 7942.503us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 951.030s 13167.478us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1771.210s 36200.034us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 151.030s 3079.790us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 242.110s 9837.961us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 242.110s 9837.961us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 951.030s 13167.478us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1521.880s 23087.054us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 296.210s 5202.343us 1 1 100.00
chip_sw_pwrmgr_smoketest 197.500s 6162.860us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 199.620s 5070.032us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 344.410s 6993.949us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 174.450s 4024.787us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1005.910s 11496.785us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 115.710s 2691.875us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 636.600s 6558.332us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 388.840s 4780.798us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 438.800s 5541.802us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 141.470s 3505.154us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 144.460s 3533.671us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 344.410s 6993.949us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 344.410s 6993.949us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 758.690s 12891.012us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 762.070s 13785.427us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 199.620s 5070.032us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 151.180s 3156.025us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 290.220s 5533.768us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 103.440s 3352.191us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 143.110s 5042.276us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 476.120s 5541.199us 1 1 100.00
chip_plic_all_irqs_10 260.710s 3945.077us 1 1 100.00
chip_plic_all_irqs_20 337.060s 4322.578us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 130.890s 3379.203us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 159.810s 3133.233us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2940.630s 15240.444us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 377.690s 6737.408us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 167.640s 3101.626us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 185.240s 3681.450us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 156.700s 3580.118us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 359.460s 5444.822us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 272.680s 5134.414us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 429.450s 8668.517us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 375.760s 7369.135us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 349.790s 6971.028us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
chip_sw_data_integrity_escalation 386.970s 6572.299us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 657.530s 7942.503us 1 1 100.00
chip_sw_sysrst_ctrl_reset 954.310s 25317.459us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 122.290s 2753.803us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 165.110s 3963.311us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 297.980s 4720.604us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 954.310s 25317.459us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 954.310s 25317.459us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2021.730s 21168.342us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2021.730s 21168.342us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 212.820s 5672.437us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2524.630s 34595.928us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 96.110s 3208.246us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 120.080s 3049.081us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 258.000s 3463.374us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 262.920s 4432.379us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 772.420s 8292.525us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4416.920s 31717.403us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1577.740s 12368.772us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 148.950s 2597.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 159.340s 3180.526us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 60.080s 2563.164us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9772.960s 71773.292us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 887.710s 6700.124us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 575.680s 15118.548us 0 1 0.00
rom_e2e_jtag_debug_dev 147.620s 4191.989us 0 1 0.00
rom_e2e_jtag_debug_rma 482.320s 14468.042us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 52.780s 2682.534us 0 1 0.00
rom_e2e_jtag_inject_dev 66.450s 3270.694us 0 1 0.00
rom_e2e_jtag_inject_rma 48.880s 2479.870us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.618s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 263.270s 3647.904us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 280.480s 2540.792us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 824.620s 5458.060us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 930.950s 7928.995us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 207.770s 3030.781us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 479.870s 4996.348us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 132.930s 2707.135us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 163.440s 3072.810us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 217.530s 5849.064us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 217.400s 4430.766us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 951.030s 13167.478us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 575.680s 15118.548us 0 1 0.00
rom_e2e_jtag_debug_dev 147.620s 4191.989us 0 1 0.00
rom_e2e_jtag_debug_rma 482.320s 14468.042us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 365.810s 5219.467us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 287.990s 6081.741us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5337.910s 38057.985us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5337.910s 38057.985us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 144.870s 3336.568us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 325.520s 4914.149us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2891.640s 18461.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 185.690s 2841.731us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 320.110s 4692.540us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.640s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 142.860s 2626.503us 1 1 100.00
chip_sw_otp_ctrl_descrambling 160.320s 2975.503us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 227.690s 4318.785us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.725s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 168.490s 3562.124us 1 1 100.00
ate_bootstrap_flash_erase 533.950s 10010.320us 0 1 0.00
ate_bootstrap_one_frame 6057.150s 44922.560us 1 1 100.00
ate_bootstrap_disjoint 9187.280s 85123.597us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 47040920780108065212531116351899839284257740147811762916093789328168290018000 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 18955130818007150527070813183922544758792955544322116139224142075833670177537 None
---- STDERR ----
Another command (pid=213102) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=214274) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 101030320615108571872258183651593443193876701748046913502463332964237789694765 None
Another command (pid=250537) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=256189) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=252435) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 14537912549352846158237305246943134441276976919508526592767950123326912983656 None
Another command (pid=254309) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=254063) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=225409) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 20885735912563352554789684957063893034487019574644567476030003577783793827086 None
---- STDERR ----
Another command (pid=218266) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 31257205299681425608700770392612443501364038265864656107872420789765120216140 None
Another command (pid=258050) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=256189) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=252435) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 18410885468078064429337408313070898428976630896993480600203475763764869094417 None
Another command (pid=236988) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=242884) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=228481) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 45089851064652692610632379990065769623234566284557306026764630473887946382871 None
---- STDERR ----
Another command (pid=235523) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 10682026657792536092748850371247303084524743048707996115983234094908933923082 None
---- STDERR ----
Another command (pid=234790) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 65311832359975410659442859823224490858355918578575683279103114783457375108915 None
Another command (pid=260398) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=289929) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=289674) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 70422081989702177840434032797627070028275425333897683704882380714555014662072 None
Another command (pid=267088) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=269689) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=280710) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 101157262186955426984665772644202318015857362311822546606974746962035133952024 None
Another command (pid=297879) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=317452) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=308103) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 45497804534622346500033962986498214421173356096383588632295379492136773634574 None
Another command (pid=252325) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=258050) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=250537) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 106952426835104382243944711017095689134972210341661745535231639504304940720135 None
Another command (pid=277920) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=259971) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=252659) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 34716727733028582087486175988697515757085353312893215865264428291680825733162 None
---- STDERR ----
Another command (pid=261740) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17807326091303800406356082075359473636845360698743078456633944067088369146333 None
Another command (pid=248170) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=218266) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=236415) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 23904349657915182129228478601251601219748515437283256607420322554152255098852 None
Another command (pid=254063) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=225409) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=246483) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 57874637274459352379961599345356784579099291623607730529836041879959436827381 None
Another command (pid=232765) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=220805) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=226840) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 115552389641912043238825669964657700169759095727275558172144879647669921868395 None
Another command (pid=228378) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=220805) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=237705) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 18607018373155600668322699307196968635849196484394093624296789183832473623216 None
Another command (pid=266347) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=266782) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=260552) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 72539353150811791458563624168026376093771567311823680071309345872005170991091 None
Another command (pid=232765) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=228378) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=220805) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 110779618414387030536098789565661295373925093140811072286134057752814669989765 None
Another command (pid=243567) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=216057) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=218266) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 98163290224588011384819934188905295376188875996665394411136426250295752269732 None
Another command (pid=217540) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=232765) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=220805) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 56252383883965356359683903043899843115450402800378274882616857759397144435554 None
---- STDERR ----
Another command (pid=213102) is running. Waiting for it to complete on the server (server_pid=209840)...
Another command (pid=214274) is running. Waiting for it to complete on the server (server_pid=209840)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 28814617754071158322755554589301682457059373865506233630707128811066512599216 367
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 79416101144987815926148689283701477494033972466802079902661628709015086521982 368
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 39178681559342227731112753278773362570795433273993816483418589374770094461914 371
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 108741747995457734430666321474847187115944414404608445102625152488110778656890 332
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 13054676427267040710847473552611437072347010698573861260461984706599450857800 332
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 51134956291658068187304367317419628718130377531093218324719395726127964096667 332
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 5 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 109242341539595711850417229911065474963694580522330924951490017031989584778336 332
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 55926533705995886537748005077123127128819311198568425576216500182063145722845 324
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 50289042870105882979605499009611644593781450692882196767750634919149922143072 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 107345146490390049074333167053346333525716382027736850632652025419187084297513 312
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 71716663020936207654246175522261982869810684051085526768457666471345181194282 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 62894410300262437872376188537131532054327355245727555904829764822075685239310 374
UVM_INFO @ 10364.310680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 112601557985839722808336781199328271184299504737053717389630393771672816315440 374
UVM_INFO @ 11225.279656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 110542437368046888122206041229288798874065863816833434237724442434722796259266 346
UVM_INFO @ 5941.230568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 3 test runs
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 13772075051788803849291821496249656603450085712477050226790266460842759522786 319
UVM_ERROR @ 5302.899000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5302.899000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 51198841353313072059423712702557935655868911089285053980275480849905005188124 330
UVM_ERROR @ 6687.040000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6687.040000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 40839423913197882426133849929188151919870552563517302123153134609513952149210 324
UVM_ERROR @ 8433.146000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8433.146000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 79061293877176470280635665753173273916641336946092038466450771446690234838178 333
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 37010783670362616340685183317051809884784867916726013207615096784099514215977 333
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 30713819395563939507123997747147594546603928134437943037878743121459492548569 333
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 85572103156274538819967117760993660546611972716118614429075364636871330909469 318
UVM_ERROR @ 3255.913856 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3255.913856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 31955537029701116061845920251563665421844409419061899352484144719063069580485 332
UVM_ERROR @ 8795.504168 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 8795.504168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 108320751275139953651198783219462529579658332727622011187069171590705189622234 222
TL item was: req: (cip_tl_seq_item@35528) { a_addr: 'h107d8 a_data: 'h69a6af44 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1b18d d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2531.107560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 15188537268585121664933143162176886896382850707555284247590399966685502853785 229
TL item was: req: (cip_tl_seq_item@31718) { a_addr: 'h1053c a_data: 'h9a9a6e77 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1b6b6 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1968.797361 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 38207027135643389484363799790366054322316317588547607648898619558806949386297 367
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 39729404875193090541440247201674422674450332479446224087437269880733087771886 330
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 19111211391064011768862797610647368606447248185226450849120001355252468002578 369
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 115416287994522446975446706309082042885594293316853627599098983500841378991624 330
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 2 test runs
rom_e2e_jtag_debug_test_unlocked0 111891511340890929877804189415522463225638514069905196500797113402320987400105 335
UVM_INFO @ 15118.547503 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 104823525630586429748428014032097217046416443789626080717598580327555216558260 335
UVM_INFO @ 14468.042085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 21733529057196934834206207120774655544541323838093274745006946504063373495104 456
UVM_INFO @ 2957.441000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 101842556458322800360588565261187134039504569068968858640430491004510407095125 325
UVM_INFO @ 3101.626440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 56464179962466525957186432402337562888743571012814720919079583860037768623023 314
UVM_INFO @ 3048.113390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 87011431518567936756949660309879394289006143799318875146246284606611653734783 347
UVM_INFO @ 6494.369278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 90786455111074961466265364834624904832754119468452675776441079632360653533160 321
UVM_ERROR @ 3072.809560 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3072.809560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 60531183177319915134927173615395984903847183159908836301952341597746296814125 287
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_rand_to_scrap 68099205675438901715736448960599068495174329509394878311543403067712401225410 318
UVM_INFO @ 26676.617181 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 95724115142995824988992875883992782395252354969268017694122839629284539382551 308
UVM_ERROR @ 2521.271392 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2521.271392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 61673682382355052686979429043265794711504952359598525073553443309609906944093 337
UVM_INFO @ 34595.927530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 87729416070448566081989004652989950687123168750360812929684918553795364957518 312
UVM_INFO @ 3276.041260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 37761162438341383981222247476917349958316690371273668376423562809813008048051 313
UVM_INFO @ 2503.767535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 33209480591273964667096247514453213204670774891638828450909213412745384570737 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 104666525008102319533338852715842546401608341943286585488428575425150604343029 348
UVM_INFO @ 3647.904024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() 1 test run
chip_sw_pwrmgr_lowpower_cancel 1973046204638136388279368449263230339307418207741493481824379640280012915510 322
UVM_INFO @ 4318.785289 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 11171971715855418317780700893358117958488503787668004595816376319899874201704 252
UVM_INFO @ 5042.275755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 27400303928984233735490225505733827294286669585032901223647979185609640764554 336
UVM_INFO @ 2563.164280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 30103654686524147656219593856546285821023148362822239864069630877886282922003 317
UVM_INFO @ 3632.206000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 84533200247789214584126817455390674329727857577036411805232963095649733753307 323
UVM_INFO @ 3343.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 88448322621710050860757184429137591290450142361501107647185816748421128231133 332
UVM_INFO @ 13873.367072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 5705961651215452028166546892967842342583423221843560824077440376191853355926 277
UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 76286039119817445942186740560142779293646888363303435229460862163819114783877 330
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20253444001167905015019742217221079820709908213048546224178144034622794621372 331
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 8072898518581921157170572455918333536558520200476176109093837981492395504177 332
UVM_ERROR @ 4917.907219 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4917.907219 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---