Simulation Results: clkmgr

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.48 %
  • code
  • 97.01 %
  • assert
  • 92.94 %
  • func
  • 81.48 %
  • line
  • 98.59 %
  • branch
  • 97.96 %
  • cond
  • 89.29 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.710s 34.411us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.760s 25.229us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 10.590s 4109.234us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.280s 57.317us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.080s 29.140us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
clkmgr_csr_aliasing 1.280s 57.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.670s 17.040us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.750s 30.444us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.820s 72.678us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 40.012us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.710s 34.411us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.050s 1125.540us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.030s 204.755us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.050s 1125.540us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 1.120s 178.608us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.730s 53.287us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.970s 335.565us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.970s 335.565us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 25.229us 1 1 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
clkmgr_csr_aliasing 1.280s 57.317us 1 1 100.00
clkmgr_same_csr_outstanding 1.160s 183.101us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 25.229us 1 1 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
clkmgr_csr_aliasing 1.280s 57.317us 1 1 100.00
clkmgr_same_csr_outstanding 1.160s 183.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.590s 2.295us 0 1 0.00
clkmgr_tl_intg_err 1.210s 69.000us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 414.670s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 414.670s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 414.670s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 414.670s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.360s 81.720us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.210s 69.000us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.050s 1125.540us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.030s 204.755us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 414.670s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.690s 37.074us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.680s 41.363us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.670s 17.317us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.830s 80.427us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.850s 82.194us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.590s 2.295us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 32.243us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.590s 2.295us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 0.790s 75.125us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 23.330s 3916.103us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 90950330196669741125180150916838224448603885855773855551366770556615534830776 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 26420014336843486288647380579907930645935668524212062886415702761186164423238 80
UVM_INFO @ 81719532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 111081114529896897964968679836410049362556200164548596855993267837747647315877 83
UVM_INFO @ 2295087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---