Simulation Results: csrng

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.48 %
  • code
  • 92.23 %
  • assert
  • 92.36 %
  • func
  • 77.84 %
  • block
  • 96.88 %
  • line
  • 97.69 %
  • branch
  • 92.17 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 8.000s 45.493us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 31.000s 43.904us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 28.000s 29.068us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 38.000s 485.492us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 32.000s 71.355us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 30.000s 27.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 28.000s 29.068us 1 1 100.00
csrng_csr_aliasing 32.000s 71.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
alerts 1 1 100.00
csrng_alert 40.000s 994.923us 1 1 100.00
err 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 33.000s 173.466us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 33.000s 173.466us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 375.000s 24955.110us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 24.000s 41.304us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 31.000s 28.215us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 76.076us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 76.076us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 31.000s 43.904us 1 1 100.00
csrng_csr_rw 28.000s 29.068us 1 1 100.00
csrng_csr_aliasing 32.000s 71.355us 1 1 100.00
csrng_same_csr_outstanding 18.000s 57.107us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 31.000s 43.904us 1 1 100.00
csrng_csr_rw 28.000s 29.068us 1 1 100.00
csrng_csr_aliasing 32.000s 71.355us 1 1 100.00
csrng_same_csr_outstanding 18.000s 57.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
csrng_tl_intg_err 5.000s 137.513us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 21.000s 14.442us 1 1 100.00
csrng_csr_rw 28.000s 29.068us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 40.000s 994.923us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 375.000s 24955.110us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 40.000s 994.923us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 375.000s 24955.110us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 40.000s 994.923us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 137.513us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
csrng_sec_cm 17.000s 123.923us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 29.000s 95.857us 1 1 100.00
csrng_err 27.000s 23.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.093s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 4927519528474068867709771195179255777211392029774153013967562607103725844834 130
UVM_INFO @ 173466454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 79015267059324291945345750300197277975927094944867491295872516310617737034999 None