Simulation Results: edn/edn0

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.43 %
  • code
  • 84.52 %
  • assert
  • 97.61 %
  • func
  • 80.16 %
  • line
  • 98.48 %
  • branch
  • 94.70 %
  • cond
  • 88.33 %
  • toggle
  • 87.84 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 18.129us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 47.262us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 14.201us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.140s 187.425us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 110.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.250s 153.445us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 14.201us 1 1 100.00
edn_csr_aliasing 1.030s 110.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 91.077us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 91.077us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 91.077us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.810s 28.062us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 42.291us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 36.492us 1 1 100.00
disable 1 2 50.00
edn_disable 0.840s 45.654us 1 1 100.00
edn_disable_auto_req_mode 0.900s 18.511us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.670s 397.733us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 27.992us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 21.084us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.270s 303.464us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.270s 303.464us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 47.262us 1 1 100.00
edn_csr_rw 0.830s 14.201us 1 1 100.00
edn_csr_aliasing 1.030s 110.801us 1 1 100.00
edn_same_csr_outstanding 0.930s 34.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 47.262us 1 1 100.00
edn_csr_rw 0.830s 14.201us 1 1 100.00
edn_csr_aliasing 1.030s 110.801us 1 1 100.00
edn_same_csr_outstanding 0.930s 34.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.830s 1072.166us 1 1 100.00
edn_tl_intg_err 1.740s 120.517us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 33.302us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 42.291us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.830s 1072.166us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.830s 1072.166us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.830s 1072.166us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.830s 1072.166us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 42.291us 1 1 100.00
edn_sec_cm 5.830s 1072.166us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 42.291us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.740s 120.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 45.320s 17392.955us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 65457584166976616222142049388339918205084563895425291808785372138694267398207 93
UVM_INFO @ 18510989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---