Simulation Results: flash_ctrl

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.95 %
  • code
  • 94.12 %
  • assert
  • 95.05 %
  • func
  • 95.67 %
  • line
  • 96.05 %
  • branch
  • 97.16 %
  • cond
  • 93.93 %
  • toggle
  • 97.73 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 78.080s 28.067us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.280s 58.428us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 11.710s 30.125us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 72.920s 33793.106us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 35.150s 1263.718us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.970s 180.742us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
flash_ctrl_csr_aliasing 35.150s 1263.718us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 4.870s 70.671us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.000s 18.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.630s 116.575us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 26.700s 48.279us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1171.730s 338359.194us 1 1 100.00
flash_ctrl_hw_rma_reset 479.690s 60134.624us 1 1 100.00
flash_ctrl_lcmgr_intg 5.230s 23.717us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1492.260s 243829.451us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 154.020s 5579.059us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 4.930s 21.695us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1609.220s 79859.030us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 57.160s 2126.693us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 11.010s 29.418us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.430s 76.267us 1 1 100.00
flash_ctrl_re_evict 14.440s 67.103us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 138.050s 1424.162us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 138.050s 1424.162us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 78.350s 16082.079us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 10.650s 116.969us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 175.100s 167.557us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 607.180s 36948.121us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 276.370s 1756.002us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 673.660s 807.393us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 4.940s 21.253us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 116.200s 8485.360us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 7.670s 37.084us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 4.810s 93.999us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 516.160s 585.243us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 62.100s 4991.800us 1 1 100.00
flash_ctrl_otp_reset 47.370s 337.381us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1171.730s 338359.194us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 54.820s 859.328us 1 1 100.00
flash_ctrl_intr_wr 35.370s 3694.937us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 160.270s 27536.614us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 114.740s 44004.778us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.370s 7893.811us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 31.500s 1289.601us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.070s 26.524us 1 1 100.00
flash_ctrl_ro_derr 80.350s 799.208us 1 1 100.00
flash_ctrl_rw_derr 133.940s 2083.219us 1 1 100.00
flash_ctrl_derr_detect 103.290s 1010.259us 1 1 100.00
flash_ctrl_integrity 352.510s 4126.120us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 8.160s 86.920us 1 1 100.00
flash_ctrl_ro_serr 70.250s 693.141us 1 1 100.00
flash_ctrl_rw_serr 119.470s 2028.580us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 35.390s 584.570us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 54.870s 1067.080us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 153.330s 13696.765us 1 1 100.00
flash_ctrl_write_word_sweep 5.780s 41.780us 1 1 100.00
flash_ctrl_read_word_sweep 5.450s 92.177us 1 1 100.00
flash_ctrl_ro 59.120s 3071.004us 1 1 100.00
flash_ctrl_rw 337.060s 22196.559us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.630s 324.959us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 537.130s 41319.448us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 14.810s 10265.533us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.870s 739.673us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 4.890s 31.469us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.660s 332.608us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.660s 332.608us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 11.710s 30.125us 1 1 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
flash_ctrl_csr_aliasing 35.150s 1263.718us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.940s 167.721us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 11.710s 30.125us 1 1 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
flash_ctrl_csr_aliasing 35.150s 1263.718us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.940s 167.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 11.490s 436.475us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
flash_ctrl_tl_intg_err 167.720s 699.465us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 167.720s 699.465us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 167.720s 699.465us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 13.190s 207.456us 1 1 100.00
flash_ctrl_wr_intg 5.540s 90.667us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 78.080s 28.067us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 47.370s 337.381us 1 1 100.00
flash_ctrl_disable 7.670s 37.084us 1 1 100.00
flash_ctrl_sec_info_access 27.640s 4077.792us 1 1 100.00
flash_ctrl_connect 4.810s 93.999us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.000s 262.849us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.790s 31.899us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.150s 170.309us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 7.670s 37.084us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 13.190s 207.456us 1 1 100.00
flash_ctrl_access_after_disable 5.040s 20.647us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 10.330s 167.632us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 7.670s 37.084us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 10.650s 116.969us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 337.060s 22196.559us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 119.470s 2028.580us 1 1 100.00
flash_ctrl_rw_derr 133.940s 2083.219us 1 1 100.00
flash_ctrl_integrity 352.510s 4126.120us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1171.730s 338359.194us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.460s 742.922us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.440s 153.518us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 5.280s 22.757us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1340.860s 1160.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 16.800s 161.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 340.220s 1788.678us 1 1 100.00